Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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04 Nov 2002
TL;DR: GA-based functional test generation techniques are proposed for behavioral and register transfer level designs to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits.
Abstract: In order to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits, GA-based functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e. register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage.
13 citations
Cites background from "Digital Systems Testing and Testabl..."
...There are deterministic approaches and symbolic approaches [14, 15, 16] for test generation that are very useful for medium or small designs....
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Patent•
NEC1
TL;DR: In this paper, a logical contradiction judgment section detects the logical state of each signal line under the implication by a first implication section and judges whether the logical states of every signal line is estimated as 0, 1, or X unless a contradiction is detected.
Abstract: To realize high-speed error propagation path extraction in a combinational circuit, a logical contradiction judgment section detects the logical state of each signal line under the implication by a first implication section and judges whether the logical state of every signal line is estimated as “0,” “1,” or “X” unless a contradiction is detected. When it is judged that logical state estimation is not completed, a U(Unknown)-state retrieval section retrieves an Unknown-state signal line whose logical state is incomplete and retrieves a signal line connected to an error propagation path through a gate. A detected signal line is decided as “0,” a decision level showing a decision frequency is increased by 1, and implication is restarted by a first implication section. It is judged that logical state estimation is completed, a failing output terminal connection related line extraction section extracts an error propagation path directly influencing a failing output terminal and outputs the route to an output unit.
13 citations
20 Oct 1996
TL;DR: What can be done before, during and after synthesis to reduce design time is described, and results that show the effects of select approaches are presented.
Abstract: This paper presents new strategies for integrating scan DFT (design for test) techniques into hierarchical synthesis methodologies to meet the challenges of system-on-a-chip ICs (integrated circuits). It describes what can be done before, during and after synthesis to reduce design time, and presents results that show the effects of select approaches.
13 citations
Cites background from "Digital Systems Testing and Testabl..."
...Scan DFT [ 2 ] is essential for many high-quality ASIC implementations....
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TL;DR: In this paper, it is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components Masking and covering relations among faults are defined and used to significantly simplify multiple fault analysis and test generation.
13 citations
25 Jun 1996
TL;DR: The selective storage of state information is shown to significantly improve the time for diagnostic fault simulation and a method to reduce the amount of information stored by choosing only a subset of the state space is described.
Abstract: Repeated fault diagnosis on large integrated circuits may often be computationally prohibitive due to expensive fault simulation requirements. Fault dictionaries can help alleviate this problem, but they may be infeasible to store because of their large sizes, and more importantly, they typically provide only a black box view of the circuit and hence almost no diagnostic flexibility. The problem occurs because dictionaries usually only store primary output information. A new approach to fault diagnosis based on state information is presented. The selective storage of state information is shown to significantly improve the time for diagnostic fault simulation. We also describe a method to reduce the amount of information stored by choosing only a subset of the state space. This approach is shown to be ideally suited for partial scan circuits whose simple structure is exploited to reduce storage requirements. Experiments on the ISCAS 89 benchmark circuits are performed to demonstrate the efficiency of the state information based diagnosis technique.
13 citations