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Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: A counter-free extended Euclidean algorithm is proposed for GF inversion and efficient systolic GF inverters are obtained, which are extendible to GF dividers and shown to be easily testable.
Abstract: Galois field (GF) computation is important in applications such as error-control coding, switching theory, and cryptography. In GF, division and inversion operations are much harder to implement in digital logic as compared with multiplication and addition operations so far as performance and hardware complexity is concerned. Although several VLSI structures for division or inversion have been proposed in the past, most of them have complex routing, nonmodular architectures, and low testability. Testability especially is an increasing concern in VLSI design. In this paper, C-testable bit-level systolic arrays for GF(2/sup m/) inversion are presented. We propose a counter-free extended Euclidean algorithm for GF inversion. Based on the algorithm, we obtain efficient systolic GF inverters, which are extendible to GF dividers. Both the bit-parallel and bit-serial inverters proposed are shown to be easily testable. For example, the bit-serial inverter requires only four test patterns regardless of the field size (or number of cells). High testability is a key advantage for the proposed GF inverters, especially in core-based VLSI system chips.
13 citations
Cites background from "Digital Systems Testing and Testabl..."
...Testability especially is an increasing concern in VLSI design [ 11 ], [12]....
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30 Jan 2001
TL;DR: Three new DFT strategies are proposed to reduce the test application time of the full scan design method by reducing the number of flip-flops on a scan path.
Abstract: As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method.
13 citations
Cites background from "Digital Systems Testing and Testabl..."
...Design for Testability Strategies Using Full/Partial Scan Designs and Test Point Insertions to Reduce Test Application Times Toshinori Hosokawa Masayoshi Yoshimura Mitsuyasu Ohta Corporate Semiconductor Development Division Matsushita Electric Industrial Co., Ltd. / Design Technology Development Department Semiconductor Technology Academic Research Center 6-16-10, Shimbashi, Minato, Tokyo 105-0004, Japan Tel:+81-3-3436-0520 Fax:+81-3-3436-0528 e-mail:hosokawa@starc.or.jp Abstract As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates....
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...…Electric Industrial Co., Ltd. / Design Technology Development Department Semiconductor Technology Academic Research Center 6-16-10, Shimbashi, Minato, Tokyo 105-0004, Japan Tel:+81-3-3436-0520 Fax:+81-3-3436-0528 e-mail:hosokawa@starc.or.jp Abstract As an LSI is on the two-dimensional…...
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01 Jan 2005
TL;DR: The experimental results presented in this paper indicate that fault coverage obtained using RTL level fault modeling has resulted in a coverage that is in close proximity with the corresponding gate-level fault coverage.
Abstract: Testing of digital circuits has traditionally been done using fault models at the gate level or below. Use of these lower level fault models adds complexity and delays testing efforts to later in the design cycle. There is a need to develop a design methodology for performing fault simulation throughout the design process, at many levels of abstraction. This work focuses on fault modeling and simulation at the register transfer (RT) level, and aims at exploring the capabilities of the stuck-at fault model in computing the fault coverage at the RT-level. The experimental results presented in this paper indicate that fault coverage obtained using RTL level fault modeling has resulted in a coverage that is in close proximity with the corresponding gate-level fault coverage
13 citations
Cites background from "Digital Systems Testing and Testabl..."
...This assumption is justified by the single testing strategy [6], which states that we should test a system often enough so that the probability of more than one fault developing between two consecutive testing experiments is sufficiently small....
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04 Jan 2003
TL;DR: A new built-in self-test (GIST) scheme for scan-based circuits is proposed for reducing energy consumption and a mapping logic is designed which modifies the state transitions of the LFSR such that only the useful vectors are generated according to a desired sequence.
Abstract: In a random testing environment, a significant amount of energy is wasted in the LFSR and in the CUT by useless patterns that do not contribute to fault dropping. Another major source of energy drainage is the loss due to random switching activity in the CUT and in the scan path between applications of two successive vectors. In this work, a new built-in self-test (GIST) scheme for scan-based circuits is proposed for reducing such energy consumption. A mapping logic is designed which modifies the state transitions of the LFSR such that only the useful vectors are generated according to a desired sequence. Further, it reduces test application time without affecting fault coverage. Experimental results on ISCAS-89 benchmark circuits reveal a significant amount of energy savings in the LFSR during random testing.
13 citations
Cites methods from "Digital Systems Testing and Testabl..."
...We assume fully isolated scan-path architecture [12], where the scan register (SCAN) is completely separated from the CUT by a buffer register (BUFFER)....
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25 May 2003
TL;DR: This is the first proposal of an efficient nonuniform sampling driver (SD) design in the open literature and promises increased equivalent sampling rates with reduced overall hardware costs of the DSP system.
Abstract: Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs of the DSP system. The equivalent sampling rate is the sampling rate that a uniform sampling device would require in order to achieve the same processing bandwidth. Equivalent bandwidths of realizable systems may well extend into the GHz range while the mean sampling rate stays in the MHz range. Current prototype systems (IECS) have an equivalent bandwidth of 1.6 GHz at a mean sampling rate of 80 MHz, achieving 40 times the bandwidth of a classic DSP system that would operate uniformly at 80 MHz. Throughout the literature on nonuniform sampling, different sampling schemes have been investigated. This paper focuses on nonuniform sampling schemes optimized for fast and efficient hardware implementation. To our knowledge, this is the first proposal of an efficient nonuniform sampling driver (SD) design in the open literature.
13 citations