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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Journal Article•DOI•
01 Sep 2007
TL;DR: A scan flip-flop is designed to observe both single event transient and single event upset (SEU) soft errors in logic VLSI systems, and the basic concepts have been validated with Verilog timing simulations.
Abstract: A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEL' soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEL soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insnlator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable.

13 citations

Journal Article•DOI•
TL;DR: This paper presents a logic restructuring technique named node addition and removal (NAR), which works by adding a node into a circuit to replace an existing node and then removing the replaced node, and applies the NAR approach to circuit minimization together with two techniques: redundancy removal and mandatory assignment reuse.
Abstract: This paper presents a logic restructuring technique named node addition and removal (NAR) It works by adding a node into a circuit to replace an existing node and then removing the replaced node Previous node-merging techniques focus on replacing one node with an existing node in a circuit, but fail to replace a node that has no substitute node To enhance the node-merging techniques on logic restructuring and optimization, we propose an NAR approach in this paper We first present two sufficient conditions that state the requirements of added nodes for safely replacing a target node Then, an NAR approach is proposed to quickly detect the added nodes by performing logic implications based on these conditions We apply the NAR approach to circuit minimization together with two techniques: redundancy removal and mandatory assignment reuse We also apply it to satisfiability (SAT)-based bounded sequential equivalence checking (BSEC) to reduce the computation complexity of SAT solving The experimental results show that our approach can enhance our prior automatic test pattern generation-based node-merging approach Additionally, our approach has a competitive capability of circuit minimization with 44 times speedup compared to a SAT-based node-merging approach For BSEC, our approach can work together with other optimization technique to save a total of approximately 39-h verification time for all the benchmarks

13 citations

Proceedings Article•DOI•
07 Oct 2009
TL;DR: Experimental results show good tradeoffs between number of observation points that need to be inserted and diagnostic resolution achieved.
Abstract: We investigate the benefit of inserting observation points in a circuit in order to improve its diagnostic resolution. The insertion of the points is done so that each fault has a unique signature on these points under at least one of the applied test patterns. The observation points are scan-like elements that serve as test-phase outputs and can be organized in and observed through one or multiple chains. Experimental results show good tradeoffs between number of observation points that need to be inserted and diagnostic resolution achieved.

13 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ..., [2], [11], [6] for an overview), such as increasing fault coverage and/or decreasing number of test patterns....

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Journal Article•DOI•
TL;DR: It is shown that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults, and a few methods are discussed that make the DBT less time consuming.

12 citations

Proceedings Article•DOI•
10 Nov 1996
TL;DR: In this paper, a generalized stuck-at fault model for sequential circuits under the selective I/sub DDQ/ test strategy is proposed, which makes a pessimistic assumption on the Boolean fault effects when the fault is activated.
Abstract: We propose a generalized stuck-at fault model for sequential circuits under the selective I/sub DDQ/ test strategy. The proposed fault model makes a pessimistic assumption on the Boolean fault effects when the fault is activated. We show that by using the proposed fault model, test sequences of higher quality can be generated and/or selected. We further propose a test vector generation and selection method for this fault model. We present results to illustrate that a high fault coverage for the proposed fault model can be achieved by a small test set under the selective I/sub DDQ/ test environment.

12 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...of ECE, University of California, Santa Barbara The second author was partially sponsored by National Science Foundation under grant MIP 9503651 expansion technique [1]....

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  • ...The parallel fault simulation technique [1] is used for fault simulation....

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