Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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13 Jun 2005
TL;DR: Effective logic soft error protection requires solutions to the following three problems: accurate soft error rate estimation for combinational logic networks; automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected.
Abstract: Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
99 citations
TL;DR: Different techniques for checking whether an asynchronous circuit has fabrication defects are surveyed, which include approaches to self-checking design, methods for test generation, design for testability, and delay test of asynchronous circuits.
98 citations
29 May 1995
TL;DR: An approximation algorithm based on an approximation algorithm for the multi-cut problem in a special type of directed networks, and a combinatorial algorithm that computes a (1 + e) approximation to the fractional optimal feedback vertex set.
Abstract: This paper deals with approximating feedback sets in directed graphs. We consider two related problems: the weighted feedback vertex set (FVS) problem, and the weighted feedback edge set problem (FES). In the FVS (resp. FES) problem, one is given a directed graph with weights on the vertices (resp. edges), and is asked to find a subset of vertices (resp. edges) with minimum total weight that intersects every directed cycle in the graph. These problems are among the classical NP-Hard problems and have many applications. We also consider a generalization of these problems: SUBSET-FVS and SUBSET-FVS, in which the feedback set has to intersect only a subset of the directed cycles in the graph. This subset contains all the cycles that go through a distinguished input subset of vertices and edges. We present approximation algorithms for all four problems that achieve an approximation factor of O(min{log τ* log log τ*, log n log log n)}, where τ* denotes the value of the optimum fractional solution of the problem at hand. For the SUBSET-FVS and SUBSET-FVS problems we also give an algorithm that achieves an approximation factor of O(log2 ‖X‖), where X is the subset of distinguished vertices and edges. This algorithm is based on an approximation algorithm for the multi-cut problem in a special type of directed networks. Another contribution of our paper is a combinatorial algorithm that computes a (1 + e) approximation to the fractional optimal feedback vertex set. Computing the approximate solution is much simpler and more efficient than general linear programming methods. All of our algorithms use this approximate solution.
96 citations
Cites background from "Digital Systems Testing and Testabl..."
...A fractional feedback vertex set of G is a function ~ : V --* [0, 1 ], such that every directed cycle, C, is "covered" by ~; that is, ~v~c t(v) >__ 1. The weight of a fractional feedback vertex set, t, is defined by ~cv w(v)....
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30 Apr 2006
TL;DR: Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation.
Abstract: High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.
96 citations
Cites methods from "Digital Systems Testing and Testabl..."
...There are two approaches to test cube generation: In the inATPG approach, logic values for some inputs of a circuit are determined only for the purpose of detecting a target fault, and the result is usually a test cube since not all inputs need to be assigned with logic values [1]....
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...In the post-ATPG approach, a fully-specified test vector or test set is given, and some bits are changed to X-bits if doing so does not affect fault coverage [7, 10]....
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...The new method for LCP test generation is based on a twopass flow as follows: Pass-1: Conventional detection-oriented ATPG is used to generate a compact test set T with satisfactory fault coverage....
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...The initial test set T is generated by a conventional detection-oriented ATPG procedure in Pass-1....
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...This paper proposed a novel algorithm for test cube generation not only for fault detection but also for capture power reduction, by introducing the concepts of capture conflict and implication stack restoration into ATPG....
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TL;DR: This paper presents a novel formulation of the debugging problem using MaxSAT to improve the performance and applicability of automated debuggers, and introduces two performance improvements to further reduce the time required to find all error sources within the design by an order of magnitude.
Abstract: As contemporary very large scale integration designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug solutions such as those based on Boolean satisfiability (SAT) enable engineers to reduce the debug effort by localizing possible error sources in the design. Unfortunately, adaptation of these techniques to industrial designs is still limited by the performance and capacity of the underlying engines. This paper presents a novel formulation of the debugging problem using MaxSAT to improve the performance and applicability of automated debuggers. Our technique not only identifies errors in the design but also indicates when the bug is excited in the error trace. MaxSAT allows for a simpler formulation of the debugging problem, reducing the problem size by 80% compared to a conventional SAT-based technique. Empirical results demonstrate the effectiveness of the proposed formulation as run-time improvements of 4.5 × are observed on average. This paper introduces two performance improvements to further reduce the time required to find all error sources within the design by an order of magnitude.
96 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Techniques based on simulation [5], path tracing [6], and binary decision diagrams [7] have been proposed in the literature to enhance the efficiency of error localization and diagnosis....
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