Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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01 Nov 1992
TL;DR: A multi-facet scan design system called SIESTA is presented that attempts to find solutions that satisfy designer goals and constraints and employs several new concepts that do not exist in other scan design systems.
Abstract: Scan design methodology has led to a range of design-for-testability techniques. However, scan techniques are not universally accepted by circuit designers because of the various overheads involved, such as chip area, performance, I/O pin count and test application time. The authors present a multi-facet scan design system called SIESTA that attempts to find solutions that satisfy designer goals and constraints. SIESTA incorporates a range of methodologies and optimization techniques that deal with the issues of partial scan, circuit partitioning, test application and scan path chaining. It employs several new concepts that do not exist in other scan design systems. >
12 citations
TL;DR: A diagnostic test generation process is described that produces a range of test sets based on a ranking of the indistinguished fault pairs according to the importance of distinguishing them based on the structural distance between faults.
Abstract: The size of a diagnostic test set is significantly larger than the size of a fault detection test set. As a result, fault detection test sets may be used for initial defect diagnosis, and diagnostic tests may be added as needed to narrow down a set of candidate defect sites. Between a fault detection test set and a full diagnostic test set there is a large range of test sets that can be used for improved (initial) diagnosis. This paper describes a diagnostic test generation process that produces such a range of test sets. The process is based on a ranking of the indistinguished fault pairs according to the importance of distinguishing them. The ranking is based on the structural distance between faults. This allows failure analysis to explore fewer and more localized areas of the circuit as the size of the diagnostic test set is increased. This paper also discusses the insertion of observation points to distinguish fault pairs that remain indistinguished by a diagnostic test set. Observation point insertion uses the ranked list of indistinguished fault pairs to ensure that a limited number of observation points will address the fault pairs that are the most important to distinguish.
12 citations
Proceedings Article•
10 Sep 2001
TL;DR: Two lost-cost solutions for providing error detection capabilities to processor-based systems are compared and the effects of SEUs and SETs is studied through simulation-based fault injection.
Abstract: In this paper two lost-cost solutions for providing error detection capabilities to processor-based systems are compared The effects of SEUs and SETs is studied through simulation-based fault injection which is used to compare the error detection capabilities of a hardware-implemented solution, based on parity code, with that of a software-implemented solution based on source-level code modification Radiation testing experiments confirmed the obtained results
12 citations
TL;DR: A unified global and local interconnect testing scheme for field programmable gate arrays is presented and an efficient computer algorithm for automatic derivation of test configurations is given.
Abstract: This paper presents a unified global and local interconnect testing scheme for field programmable gate arrays. Adjacency graphs are used to model interconnect resources and their test requirements, and an efficient computer algorithm for automatic derivation of test configurations is given. A device configuration generation tool was developed to reduce the test development cost.
12 citations
Cites background from "Digital Systems Testing and Testabl..."
...Assumption 1: When a logic value, 0 or 1, is applied to one end of a wire that contains stuck-open fault(s), the wire presents a logic 0 at the other end [ 8 ]....
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...This assumption covers a wide range of bridging behavior of wire segments under various technologies [ 8 ]....
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Patent•
28 Aug 2014
TL;DR: In this article, an integrated circuit device including: a first layer including first transistors, a second metal layer overlaying the first layer, and a connection path between the second transistors and the second metal layers, where the connection path includes at least one through-layer via, and where the throughlayer via has a diameter less than 150 nm.
Abstract: An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.
12 citations