Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: This paper presents a method of primitive fault identification and test generation for combinational and nonscan sequential circuits that uses the concept of sensitizing cubes to obtain input vectors that statically sensitize primitive faults in combinational circuits.
Abstract: This paper presents a method of primitive fault identification and test generation for combinational and nonscan sequential circuits. It uses the concept of sensitizing cubes to obtain input vectors that statically sensitize primitive faults in combinational circuits. The same technique is used to identify combinationally primitive faults in the next-state and output logic of sequential circuits. Such faults are primitive if and only if the fault effects on paths to state variable flip-flops can be propagated to a primary output (PO). Test sequences, including initializing sequences from a reset state and sequences that propagate fault effects from flip-flops to POs, are generated for primitive faults, wherever possible. The proposed method has been implemented and used to derive tests for primitive faults in the ISCAS'89 and MCNC'91 benchmark circuits. It was able to find all primitive faults and also obtain robust tests for a large fraction of them when the circuits were treated as combinational. When the same circuits were treated as nonscan sequential circuits, all primitive faults could not be found because fault propagation had to be limited to a relatively small number of time frames.
11 citations
Cites background from "Digital Systems Testing and Testabl..."
...frame expansion [20] with only minor changes to account for fault reactivation during propagation....
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Patent•
15 Apr 2013
TL;DR: In this article, the authors propose a method of designing a 3D integrated circuit, the method including: performing placement using a 2D placer, performing placement for at least a first strata and a second strata, and then performing routing and completing the physical design of said 3D Integrated Circuit.
Abstract: A method of designing a 3D Integrated Circuit, the method including: performing placement using a 2D placer, performing placement for at least a first strata and a second strata, and then performing routing and completing the physical design of said 3D Integrated Circuit.
11 citations
30 Apr 2006
TL;DR: This paper proposes two new theorems by making use of the generalized dominance relations exhibited by a pair of faults by employing a fault-independent analysis and proposing heuristics to reduce the number of fault-pair comparisons required.
Abstract: Fault collapsing of a fault-set helps in obtaining smaller test-sets as well as in reducing fault-simulation times. In this paper, we propose two new theorems by making use of the generalized dominance relations exhibited by a pair of faults. In order to learn several unique requirements for the faults in a low-cost manner, we employ a fault-independent analysis and propose heuristics to reduce the number of fault-pair comparisons required. Experimental results on ISCAS85, 89 & 93 benchmarks show that significantly more faults can be collapsed as compared to the existing methods, with smaller run-times in many cases. For most circuits, collapsing to less than 30% of the total number of faults is achieved.
11 citations
Cites background from "Digital Systems Testing and Testabl..."
...However, this needs to be exercised with caution [1,17]....
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...Fault collapsing has been widely studied in the past due to the potential benefits obtained during test generation [1, 2]....
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12 Oct 1997
TL;DR: An automatic test generation (ATG) based technique is presented to efficiently generate tight lower bounds of the maximum instananeous power for CMOS sequential circuits under non-zero gate delays and is superior to the traditional simulation-based technique in both speed and performance.
Abstract: With the high demand for reliability and performance, accurate estimation of maximum instantaneous power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and to optimize the power and ground routing. Unfortunately, the problem of determining the input patterns to induce maximum current, and hence, the maximum power, is NP-complete. Even for circuits with small number of primary inputs (PIs), it is CPU time intensive to conduct efficiently search in the input vector space. The authors present an automatic test generation (ATG) based technique to efficiently generate tight lower bounds of the maximum instananeous power for CMOS sequential circuits under non-zero gate delays. Power dissipation due to spurious transitions has been considered by incorporating static timing analysis into the estimation process. Experiments were performed on ISCAS and MCNC benchmarks. Results show that the ATG-based technique is superior to the traditional simulation-based technique in both speed and performance. On average, for sequential circuits having over 10,000 gates (ISCAS-89 benchmarks), the ATG-based approach executes 981 times faster, and generates a lower bound which is 1.8 times better compared to simulation based approaches.
11 citations
TL;DR: An exact unified analytical expression for the transient (and the steady state) behavior of the Aliasing Error Probability (AEP) of signature analysis testing using single-input external- and internal-XOR LFSR is deduced.
Abstract: In this paper, an exact unified analytical expression for the transient (and the steady state) behavior of the Aliasing Error Probability (AEP) of signature analysis testing using single-input external- and internal-XOR LFSR is deduced. The expression, contrary to what is known in the literature, uses the leftmost bit of the LFSR.
11 citations
Cites background from "Digital Systems Testing and Testabl..."
...The problem of calculating the AEP of LFSRs in signature analysis testing has invoked a considerable amount of research in the past decade [3], [4], [5], [6]....
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