Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Patent•
02 Dec 1993TL;DR: In this article, the authors propose a method for disabling one or more modules that are not under test and enabling those modules which are to be tested, and the enabled modules are then tested sequentially, preferably using output from the disabled modules.
Abstract: An integrated circuit includes a plurality of interconnected circuit modules having memory elements and logic elements therein. The modules collectively perform the operations of the integrated circuit. However, rather than testing the entire circuit and limiting the degree of fault coverage, individual modules can be tested on a module by module basis. To facilitate testing at the module level, the circuit includes a plurality of control cells connected to respective ones of the modules. Each of the control cells preferably includes a shift register latch for retaining a data signal corresponding to whether the respective module is to be sequentially tested or temporarily disabled. The control cells further comprise a pass-through transistor network for passing the system clock to one or more of the modules under test and for withholding the clock from the modules not under test. The method of the present invention includes steps for disabling one or more modules which are not under test and enabling those modules which are to be tested. The enabled modules are then tested sequentially, preferably using one or more outputs from the disabled modules. Testing of the integrated circuit occurs on a module by module basis until all modules are tested.
11 citations
04 Sep 2004
TL;DR: This tutorial aims to introduce circuit designers to the problems of making integrated circuits more testable, and the possibilities offered by techniques using small circuit modifications are specially focused, as the means to improve circuit testability, and thus the fault coverage.
Abstract: This tutorial aims to introduce circuit designers into the problems of making integrated circuits more testable. An efficient test procedure for a complex, mixed-signal Application Specific Integrated Circuit (ASIC), must take several factors into consideration: stimuli generation, sufficient access, single test output, simple measurement set and system-level decomposition.These factors worth attention for specific circuits classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. Attention will be paid to integrated filters and integrated analog-to-digital and digital-to-analog converters, as they are today the main analog and mixed-signal cores found in state-of-the-art complex Systems-on-Chip (SoCs). In particular, the possibilities offered by techniques using small circuit modifications will be specially focused, as the means to improve circuit testability, and thus the fault coverage, while avoiding at most to degrade the performance of the final electronic system. Practical silicon examples will be presented, trying to give a flavour on the pros and cons that design for test is offering nowadays to integrated circuit designers.To meet the goals stated above, the following topics are addressed in this tutorial: introduction to mixed-signal test (main test concepts, digital vs. analog testing, test practice in integrated circuit industry, design and test inter-relations), testing approaches (fault-based, specification-based, techniques for testing filters, techniques for testing converters), and design-for-test techniques (enhancing testability, built-in self-test and on-line test).This tutorial is intended to professionals interested in analog and mixed-signal integrated circuits in general: designers interested in how to consider test in early design phases, test engineers interested in incorporating test within the design flow, and academics involved in research and education on test procedures and strategies.
11 citations
TL;DR: This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD).
Abstract: This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits The method is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD) This method allows designers to perform dynamic fault location of stuck-at faults in large circuits, and eliminates the need for large storage required by a software-based fault dictionary In fact, the approach is a pure hardware solution to fault diagnosis We demonstrate the feasibility of the method in terms of hardware resources and diagnosis time by experimenting with ISCAS85 and ISCAS89 circuits The emulation-based diagnosis method speeds up the diagnosis process by an order of magnitude compared to the software-based fault diagnosis This speed-up is important, especially, when the on-line diagnosis of safety---critical systems is of concern
11 citations
Journal Article•
TL;DR: Three-level networks obtained from single-rail-input OR-ANDEXOR expressions are presented and a more easily testable realization is proposed which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant.
Abstract: It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n + 4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-ANDEXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-ANDEXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 ≤ r ≤ n). We show that only (r + n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network. key words: logic synthesis, exclusive-or, single stuck-at fault, easily testable realization
11 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...This paper deals with the single stuck-at fault model because it covers a wide range of possible faults and has been most widely studied [1]....
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...If adding r extra primary inputs requires considerable hardware costs, the scan path technique [1] can be used instead....
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...Recently design techniques that are easily testable have been widely used to reduce the time for testing [1]....
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03 Nov 1997
TL;DR: The effect of one class of "possible-detect" faults and the implicit ability of a test pattern set in detecting such faults on real hardware are discussed.
Abstract: Digital designs, implemented in CMOS technology, have increasingly used tri-state logic (pass gates) to increase clock speed. It is also known that tri-state logic based designs have poor testability, as measured by the single stuck-at fault model, due to the proliferation of "possible-detect" faults. Design for test techniques that have been developed to address testability issues with tri-state logic designs, often incur hardware and cycle-time overheads. In this paper, we discuss the effect of one class of "possible-detect" faults and the implicit ability of a test pattern set in detecting such faults on real hardware.
11 citations