Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: All multiple stuck-at faults occurring on a parity tree can be completely detected using test patterns provided by the identity matrix plus zero vector, including all multiple general bridging faults.
Abstract: Parity checkers are widely used in digital systems to detect errors when systems are in operation Since parity checkers are monitoring circuits, their reliability must be guaranteed by performing a thorough testing In this work, multiple fault detection of parity checkers is investigated We have found that all multiple stuck-at faults occurring on a parity tree can be completely detected using test patterns provided by the identity matrix plus zero vector The identity matrix contains 1's on the main diagonal and 0's elsewhere; while the zero vector contains 0's The identity matrix vectors can also detect all multiple general bridging faults, if the bridgings result in a wired-AND effect However, test patterns generated from the identity matrix and binary matrix are required to detect a majority of the multiple bridging faults which yield wired-OR connections Note that the binary matrix contains two 1's at each column of the matrix >
11 citations
15 May 2002
TL;DR: The concept of a multi-valued logic simulator for bridging faults in sequential circuits, where different models for the handling of intermediate values in flip flops on the digital design level can be integrated, is presented.
Abstract: We present the concept of a multi-valued logic simulator for bridging faults in sequential circuits. Different models for the handling of intermediate values in flip flops on the digital design level can be integrated and result in an expected realistic behavior area for bridging faults. Several experimental results are given to underline properties and advantages of the simulation technique.
11 citations
Cites background from "Digital Systems Testing and Testabl..."
...The wired and the dominant models [1], though realistic in TTL, are no longer valid in CMOS [10, 5]....
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01 Jun 1999
TL;DR: The approach is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the combinational circuit under diagnosis (CUD), which eliminates the need for large storage required by a software based fault diagnosis.
Abstract: In this paper, we introduce a new approach for locating and diagnosing faults in combinational circuits. The approach is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the combinational circuit under diagnosis (CUD). This approach eliminates the need for large storage required by a software based fault diagnosis. In this paper, we show the approach's feasibility in terms of hardware resources, speed, and how it compares with software based techniques.
11 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Fault location (Diagnosis) techniques are classi ed into two main groups based on the analysis performed; (1) cause-e ect analysis [2]; (2) e ect-cause analysis [7,10]....
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Patent•
16 Mar 2012
TL;DR: In this paper, a method for fabricating an integrated device, including, overlying a first crystalline layer onto a second layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of them has been transferred by performing an atomic species implantation.
Abstract: A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors.
11 citations
11 Nov 1991
TL;DR: A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator and a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback make it possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with as many as hundreds of thousands of M OS transistors in a workstation environment.
Abstract: A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator is presented along with a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback. Simulation speedup of 3N over SPICE-like simulators has been observed, where N is the number of transistors. The simulator is able to simulate circuits as large as 235000 transistors in 10 min real time. Also presented is a novel approach to fast hot-carrier reliability simulation. These methods make it possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with as many as hundreds of thousands of MOS transistors in a workstation environment. >
11 citations