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Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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27 Apr 2003
TL;DR: In this article, built-in test pattern generation (TPG) mechanisms that enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead are presented.
Abstract: In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.
11 citations
Cites background from "Digital Systems Testing and Testabl..."
...] As can be observed, for the Type–2 LFSR, the sequence in stage c2 is a shift–by–12 version of c3, the sequence in stage c1 is a shift–by–1 version of c2, the sequence in stage c0 is a shift–by–1 version of c1, so the inherent channel separations in this case are [12,1,1]....
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..., [1]), or of a Cellular Automaton (CA)....
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13 May 2001
TL;DR: The results validate the feasibility of the proposed in-system testing scheme and utilize the existing features of FPGA design tools and developed a tool to automate the required interconnect routing.
Abstract: This paper presents the design and implementation of a parity-based built-in self-test (BIST) scheme for interconnects of field programmable gate arrays (FPGAs). The self-test is achieved by using a set of proposed test configurations (TCs). Design flows were developed to enable the implementation. We utilized the existing features of FPGA design tools and developed a tool to automate the required interconnect routing. The conventional FPGA design flow was used to implement the BIST circuitry. A complete FPGA TC was presented. The pre- and post-mapping simulations were conducted. The results validate the feasibility of the proposed in-system testing scheme.
11 citations
25 May 2009
TL;DR: A new hierarchical two-step method of X- masking is presented to achieve a high observability of scan cells and to reduce the overhead for X-masking.
Abstract: In this paper we consider the test of large circuits. Due to the increasing number of scan chains of industrial designs and due to the limited recourses of the ATE-equipment the compression ratio of the test responses increases. A second issue are undefined states (X-values). In the presence of X-values during test a considerable number of the scan cells cannot be observed at the compressed outputs. We present a new hierarchical two-step method of X-masking to achieve a high observability of scan cells and to reduce the overhead for X-masking. For every scan-shift cycle the generated X-mask is either set to be active or not. By this method the number of X-values at the compacted outputs is considerably reduced. The remaining small number of X-values can be tolerated by an X-tolerant compactor. To implement this method a hierarchically configurable register is used.
11 citations
16 Oct 2000
TL;DR: A new methodology for developing systematic and automatic test generation algorithms for multipoint protocols and uses an extended finite state machine (FSM) model of the protocol PIM to circumvent the state space explosion problem.
Abstract: We present a new methodology for developing systematic and automatic test generation algorithms for multipoint protocols. These algorithms attempt to synthesize network topologies and sequences of events that stress the protocol's correctness or performance. This problem can be viewed as a domain-specific search problem that suffers from the state space explosion problem. One goal of this work is to circumvent the state space explosion problem utilizing knowledge of network and fault modeling, and multipoint protocols. The two approaches investigated are based on forward and backward search techniques. We use an extended finite state machine (FSM) model of the protocol. The first algorithm uses forward search to perform reduced reachability analysis. Using domain-specific information for multicast routing over LAN, the algorithm complexity is reduced from exponential to polynomial in the number of routers. This approach, however, does not fully automate topology synthesis. The second algorithm, the fault-oriented test generation, uses backward search for topology synthesis and uses backtracking to generate event sequences instead of searching forward from initial states. Using these algorithms, we have conducted studies for correctness of the multicast routing protocol PIM.
11 citations
Cites background from "Digital Systems Testing and Testabl..."
...line in the circuit is always at logic ‘1’ or ‘0’. Test vectors are generated based on a model of the circuit and a given fault model. Test vector generation can be faultindependent or fault-oriented [46] [47]. In the fault-oriented process, the two fundamental steps in generating a test vector are to activate (or excite) the fault, and to propagate the resulting error to an observable output. Fault e...
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01 May 2017
TL;DR: Volume diagnosis data mining for root cause identification based on statistical methods is used to reduce turnaround time and cost to speed up the process of systematic defect identification.
Abstract: With decreasing feature sizes and increasing complexity of fabrication processes for manufacturing VLSI semiconductor devices, more systematic defects occur at the advanced technology nodes. Product yield ramp up is mostly determined by how fast systematic defects are identified and fixed. Given the long times and expense of physical failure analysis (PFA), use PFA on a large number of failing devices to find systematic defects is becoming infeasible. For this reason, volume diagnosis data mining for root cause identification based on statistical methods is used to reduce turnaround time and cost to speed up the process of systematic defect identification. The identified root cause information not only can be used to improve yield analysis but also can reduce PFA cost by focusing on failing devices with systematic defects.
11 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...4) Scenario 4 This scenario is modified from Scenario 1 by changing parameter d) from [1-100] to [1-1K] to have more unpicked card decks per drawn number....
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...INTRODUCTION Scan diagnosis also called logic diagnosis [1-6] is used to determine the defect locations and defect mechanism for a given failing device and the scan test patterns used....
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