Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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25 Apr 1994
TL;DR: Test quality measures that quantify the completeness of a functional test are proposed that were evaluated using an RTL model of a RISC processor and a combinational circuit.
Abstract: Describes test quality measures that quantify the completeness of a functional test. The measures are based on exercising a functional model of the unit with the given set of test sequences. Two metrics are proposed: the control-flow coverage (FC1) indicates how completely the logical flow of the functional model is traversed, and the data path coverage (FC2) indicates how completely the data paths have been exercised over a specified set of observable values. The metrics were evaluated using an RTL model of a RISC processor and a combinational circuit. >
10 citations
02 Apr 2000
TL;DR: All internal stuck-at faults which are detectable by Boolean testing, can be represented as pin-faults, which makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time.
Abstract: This paper addresses the problem of fault collapsing in asynchronous circuits. We investigate different transistor-level implementations of some basic elements that are used in delay-insensitive asynchronous circuit designs, and analyze them in the presence of single stuck-at-faults. From this analysis, we conclude that all internal stuck-at faults which are detectable by Boolean testing, can be represented as pin-faults. This abstraction makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time. We show how this fault model, called DUDES, can be used for fault collapsing to reduce the size of fault lists at the logic level, thereby reducing the simulation time even further. We set the basis for a formal technique for deriving equivalence relationships among the faults under consideration, using trace expressions, and illustrate that this formal technique also supports fault collapsing at the system level. This framework can be expanded to a theory of fault abstraction and collapsing for asynchronous circuits that can reduce the complexity of rest pattern generation and fault simulation.
10 citations
Cites background from "Digital Systems Testing and Testabl..."
...This abstraction makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time....
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02 Dec 2001
TL;DR: The structure of PFLD is derived and a new sequential fuzzy hardware design methodology is developed, and the capability for synthesizing each of the categories is shown to ease design process.
Abstract: A programmable fuzzy logic device (PFLD) is proposed for sequential fuzzy hardware design. Fuzzy automata are classified into ten categories according to properties of inputs, states, and time intervals. Among the categories, a most general one called generalized fuzzy automata (GFA) is defined and its powerfulness is proven. From the GFA, we derive the structure of PFLD and develop a new sequential fuzzy hardware design methodology. The PFLD capability for synthesizing each of the categories is shown to ease design process. A PFLD includes generic LR fuzzy cells, current memories, and common analog current mode devices. The novel switch-current scheme makes target sequential fuzzy logic circuits possess high performance, low power, and compactness advantages. Two well-known fuzzy state machines, a fuzzy temporal knowledge system and a fuzzy feedback controller, as examples are realized with PFLDs.
10 citations
27 Apr 2015
TL;DR: A new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects is presented.
Abstract: The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors Traditional delay diagnosis algorithm has a limited support for cell internal timing related failures based on transition delay faults, and tends to provide a large suspect list It cannot provide the precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning In this work, we present a new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects Preliminary results for real silicon failures show that significant diagnosis resolution improvement can be achieved by the proposed method
10 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Scan diagnosis [1], [3], [15], [16] is used to determine the most likely faulty locations and fault types for a given failing device based on scan failures....
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TL;DR: The authors investigate the testability of recently introduced three-level logic forms sum of pseudoproducts (SPP), which allow the representation of Boolean functions with much shorter expressions than two-level forms.
Abstract: Full testability is a desirable property for a minimal logic network. The classical minimal two-level sum of products (SOP) networks are fully testable in some standard fault models. In this paper, the authors investigate the testability of recently introduced three-level logic forms sum of pseudoproducts (SPP), which allow the representation of Boolean functions with much shorter expressions than two-level forms. The authors study their testability under static fault models (FMs), i.e., the stuck-at-fault model (SAFM) and the cellular fault model (CFM). For SPP networks, several minimal forms can be considered. While full testability can be proven in the SAFM for some forms, SPP networks in the CFM are shown to contain redundancies. Finally, the authors propose a method for transforming nontestable networks into testable ones. In the SAFM, the resulting irredundant networks are still minimal. The experimental results are given to demonstrate the efficiency of the approach
10 citations
Cites background from "Digital Systems Testing and Testabl..."
...In the space {0, 1}n, the number of different 2-EXOR factors with exactly two literals is 2 · (n 2 ) = n(n − 1)....
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