scispace - formally typeset
Search or ask a question
Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
More filters
Proceedings ArticleDOI
01 Nov 2016
TL;DR: This paper formulates the diagnostic test generation problem under this scenario with the goal of simplifying the test application process for diagnostic tests, taking into consideration that different units require different diagnostic tests.
Abstract: A complete industrial defect diagnosis flow for yield learning includes the use of diagnostic tests. Diagnostic tests improve the ability of a defect diagnosis procedure to provide accurate diagnosis results. Because of the costs involved, diagnostic test generation is carried out only for units where the results of defect diagnosis based on a fault detection test set are not accurate enough. This paper formulates the diagnostic test generation problem under this scenario with the goal of simplifying the test application process for diagnostic tests, taking into consideration that different units require different diagnostic tests. The parameters that the problem formulation targets are the numbers of diagnostic tests for the individual units, and the total number of diagnostic tests for all the units. A lower total number of diagnostic tests increases the similarity between the diagnostic test sets for the individual units. With similar diagnostic test sets, the units are partitioned into groups such that all the units in a group are tested using the same diagnostic test set. The paper describes a diagnostic test generation procedure that uses dynamic test compaction to optimize these parameters.

10 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...A defect diagnosis procedure analyzes a faulty output response of a unit in order to produce information about the defects that are present in the unit [1]....

    [...]

Book
23 Oct 2009
TL;DR: Whatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilog full power and use it to the fullest.
Abstract: The Definitive, Up-to-Date Guide to Digital Design with SystemVerilog: Concepts, Techniques, and CodeTo design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)and todays most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it.Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilogfrom modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org.Coverage includesUsing electronic design automation tools with programmable logic and ASIC technologiesEssential principles of Boolean algebra and combinational logic design, with discussions of timing and hazardsCore modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkersSequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliersDesigning finite state machines: from ASM chart to D flip-flops, next state, and output logicModeling interfaces and packages with SystemVerilogDesigning testbenches: architecture, constrained random test generation, and assertion-based verificationDescribing RTL and FPGA synthesis modelsUnderstanding and implementing Design-for-TestExploring anomalous behavior in asynchronous sequential circuitsPerforming Verilog-AMS and mixed-signal modelingWhatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilogs full power and use it to the fullest.

10 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...n_reset) begin mdr <= 0; mar <= 0; mem[0] <= {LOAD, {(WORD_W-OP_W-3){1’b0}},3’d4}; mem[1] <= {ADD, {(WORD_W-OP_W-3){1’b0}},3’d5}; mem[2] <= {STORE,{(WORD_W-OP_W-3){1’b0}},3’d6}; mem[3] <= {BNE, {(WORD_W-OP_W-3){1’b0}},3’d7}; mem[4] <= 2; mem[5] <= 2; mem[6] <= 0; mem[7] <= 0; for (i = 8; i < (1<<(WORD_W-OP_W)); i+=1) mem[i] <= 0; end else if (bus....

    [...]

  • ...always_comb begin z[0] = ̃a[0] & ̃a[1] & ̃a[2]; z[1] = a[0] & ̃a[1] & ̃a[2]; z[2] = ̃a[0] & a[1] & ̃a[2]; z[3] = a[0] & a[1] & ̃a[2]; z[4] = ̃a[0] & ̃a[1] & a[2]; z[5] = a[0] & ̃a[1] & a[2]; z[6] = ̃a[0] & a[1] & a[2]; z[7] = a[0] & a[1] & a[2]; end...

    [...]

  • ...assign y = s[0] ? a : 1’bZ; assign y = s[1] ? b : 1’bZ; assign y = s[2] ? c : 1’bZ; assign y = s[3] ? d : 1’bZ; assign y = s[4] ? e : 1’bZ; endmodule These two models have the same functionality when simulated ....

    [...]

Journal ArticleDOI
TL;DR: It is demonstrated that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns.
Abstract: Autonomous circuits such as linear feedback shift registers (LFSRs) and cellular automats are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuit-under-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSRs and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults.

10 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...For simplicity, we concentrate on the configuration of Fig. 1 and assume that distributed test generators [ 25 ] are used, one for each circuit in a system....

    [...]

Journal ArticleDOI
TL;DR: This article analyzes the impact of manufacturing and physical defects across all layers of the bio-chip architectures and proposes a graph theory-inspired formulation for maximizing the fault coverage through test point insertion.
Abstract: Microfluidic very large scale integration (mVLSI) plays a crucial role for designing point-of-care systems. This article analyzes the impact of manufacturing and physical defects across all layers of the bio-chip architectures and proposes a graph theory-inspired formulation for maximizing the fault coverage through test point insertion. This represents a worthwhile contribution to design-for-testability of mVLSI systems. —Paul Bogdan, University of Southern California

10 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...Algorithm 1: Proposed Algorithm for Test Point Insertion Input: Circuit C(LG,W ), Test Set T , Target fault coverage η Output: Set of Test Points returned by GreedySetCover Let Si be the set of faults detected on wire wi ∈W over 1 the entire test set T ; Perform deductive fault simulation [4] of C for all test 2 vectors and compute Si for each wi ∈W ; Let U be the set of all possible faults inside C; 3 Let S = {S1,S2, ....

    [...]

  • ...We propose to implement the BIST using a linear-feedback-shift-register (LFSR) [4], as shown in Figure 6(a), constructed using pneumatic flip-flops....

    [...]

  • ...We propose to implement the BIST using a linear-feedback-shift-register (LFSR) [4], as shown in Figure 6(a), constructed using pneumatic flip-flops....

    [...]

  • ...The input Test Set contains the test vectors generated by the automatic test pattern generation algorithm [4]....

    [...]

  • ...Our DFT scheme is novel compared to existing DFT schemes for VLSI [4] because mVLSI biochips have two parts (flow and control) Con In...

    [...]

01 Jan 2006
TL;DR: It is argued that it is practical and efficient to define application area specific system level fault models to handle the growing size and complexity of testing of digital systems.
Abstract: In this paper we make a case for moving the level of test pattern generation for fabrication faults to the system level. Like many other researchers we feel it is necessary to handle the growing size and complexity of testing of digital systems. As the first step in this direction, system level fault models must be defined. Unlike logic level stuck-at fault models it is hard to define general fault models at the system level. In this paper, we argue that it is practical and efficient to define application area specific system level fault models. A NoC switch is used as a case study to explain the idea of such system level fault models. We propose two metrics to evaluate the efficiency of system level fault models. We also propose a method for generation of test patterns using system level fault models. Our initial evaluation experiments show that the test patterns generated using the proposed system level faults have much higher fault coverage than purely random test patterns but lower coverage than test pattern generated on actual implementation using the PODEM algorithm. The results of this case study demonstrate that application area specific system level fault models have a good potential for testing complex systems.

10 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...An analysis of how bit stuck-at faults at behavior level maps to RT-level faults is shown in [8]....

    [...]