Digital Systems Testing and Testable Design
Citations
10 citations
Cites methods from "Digital Systems Testing and Testabl..."
...A defect diagnosis procedure analyzes a faulty output response of a unit in order to produce information about the defects that are present in the unit [1]....
[...]
10 citations
Cites background from "Digital Systems Testing and Testabl..."
...n_reset) begin mdr <= 0; mar <= 0; mem[0] <= {LOAD, {(WORD_W-OP_W-3){1’b0}},3’d4}; mem[1] <= {ADD, {(WORD_W-OP_W-3){1’b0}},3’d5}; mem[2] <= {STORE,{(WORD_W-OP_W-3){1’b0}},3’d6}; mem[3] <= {BNE, {(WORD_W-OP_W-3){1’b0}},3’d7}; mem[4] <= 2; mem[5] <= 2; mem[6] <= 0; mem[7] <= 0; for (i = 8; i < (1<<(WORD_W-OP_W)); i+=1) mem[i] <= 0; end else if (bus....
[...]
...always_comb begin z[0] = ̃a[0] & ̃a[1] & ̃a[2]; z[1] = a[0] & ̃a[1] & ̃a[2]; z[2] = ̃a[0] & a[1] & ̃a[2]; z[3] = a[0] & a[1] & ̃a[2]; z[4] = ̃a[0] & ̃a[1] & a[2]; z[5] = a[0] & ̃a[1] & a[2]; z[6] = ̃a[0] & a[1] & a[2]; z[7] = a[0] & a[1] & a[2]; end...
[...]
...assign y = s[0] ? a : 1’bZ; assign y = s[1] ? b : 1’bZ; assign y = s[2] ? c : 1’bZ; assign y = s[3] ? d : 1’bZ; assign y = s[4] ? e : 1’bZ; endmodule These two models have the same functionality when simulated ....
[...]
10 citations
Cites methods from "Digital Systems Testing and Testabl..."
...For simplicity, we concentrate on the configuration of Fig. 1 and assume that distributed test generators [ 25 ] are used, one for each circuit in a system....
[...]
10 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Algorithm 1: Proposed Algorithm for Test Point Insertion Input: Circuit C(LG,W ), Test Set T , Target fault coverage η Output: Set of Test Points returned by GreedySetCover Let Si be the set of faults detected on wire wi ∈W over 1 the entire test set T ; Perform deductive fault simulation [4] of C for all test 2 vectors and compute Si for each wi ∈W ; Let U be the set of all possible faults inside C; 3 Let S = {S1,S2, ....
[...]
...We propose to implement the BIST using a linear-feedback-shift-register (LFSR) [4], as shown in Figure 6(a), constructed using pneumatic flip-flops....
[...]
...We propose to implement the BIST using a linear-feedback-shift-register (LFSR) [4], as shown in Figure 6(a), constructed using pneumatic flip-flops....
[...]
...The input Test Set contains the test vectors generated by the automatic test pattern generation algorithm [4]....
[...]
...Our DFT scheme is novel compared to existing DFT schemes for VLSI [4] because mVLSI biochips have two parts (flow and control) Con In...
[...]
10 citations
Cites background from "Digital Systems Testing and Testabl..."
...An analysis of how bit stuck-at faults at behavior level maps to RT-level faults is shown in [8]....
[...]