Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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01 Aug 2015
TL;DR: This paper summarizes the different available test methodologies for asynchronous and globally-asynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses and gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.
Abstract: Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globally-asynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.
10 citations
Cites background from "Digital Systems Testing and Testabl..."
...Additionally, a fault within redundant logic can mask other faults which consequently also cannot be detected [2]....
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08 Nov 2005
TL;DR: Experimental results for different degrees show that GLFSRs are preferable in both hardware cost and fault Coverage, and compare CA with phase shifters (CAPSs) andGLFSRs without phase shifter in terms of the minimum inter-channel separation that they achieve and the overall XOR cost for each construction.
Abstract: In this paper, we investigate the use of Galois LFSRs (GLFSRs) as test pattern generators in BIST schemes that employ multiple scan chains. Current schemes use LFSRs or cellular automata (CA) with additional phase shifters to provide guaranteed minimum phase shifts between successive scan chains and also impose an upper bound on the number of taps for the XOR gate of each phase shifter. We compare CA with phase shifters (CAPSs) and GLFSRs without phase shifters in terms of the minimum inter-channel separation that they achieve and the overall XOR cost for each construction. Experimental results for different degrees show that GLFSRs are preferable in both hardware cost and fault coverage
10 citations
26 Apr 2004
TL;DR: A model by which standard tests for stuck-at-faults can be used to detect interconnect breaks in a circuit is proposed and it is shown that the worst case of detection is when the bias voltage is the same as the logic threshold voltage.
Abstract: An interconnect break is a break that occurs in the interconnect wiring, which results in logic gate inputs being disconnected from the drivers and causes the wire to float. Interconnect breaks are the most common types of breaks in modern $CMOS$ integrated circuits, so testing and detecting these breaks has become very important. This paper proposes a model by which standard tests for stuck-at-faults can be used to detect interconnect breaks in a circuit. We do a worst-case analysis of the detection of these breaks and calculate the minimum number of test vectors required to detect breaks with a specified confidence level, using n-detection principles. To enhance the understanding of the breaks in the circuit, we present a statistical model based on the length distribution of the wires surrounding the floating wire where the break occurs. From the model we compute the detection probabilities of such breaks and show that the worst case of detection is when the bias voltage is the same as the logic threshold voltage.
10 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Now if dn is the n-step detection probability [1] that we detect a break f (at least once) by applying n sa0 and n sa1 tests with P (not detected | sa0 test) = α′ and P (not detected | sa1 test) = β′, then dn = 1 − (α′β′)n....
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...This is justified because the test length that is long enough to detect the most difficult break with probability c will detect any other break f with dn ≥ c [1]....
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TL;DR: A new methodology to assess the vulnerability of a circuit to malicious fault attacks, taking into account built-in protection mechanisms, is described, based on accurate modeling of fault effects and detection status expressed by Boolean satisfiability (SAT) formulas.
Abstract: Vulnerability to malicious fault attacks is an emerging concern for hardware circuits that are employed in mobile and embedded systems and process sensitive data. We describe a new methodology to assess the vulnerability of a circuit to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and detection status expressed by Boolean satisfiability (SAT) formulas. Vulnerability is quantified based on the number of solutions of these formulas, which are determined by an efficient #SAT solver. We demonstrate the applicability of this method for design space exploration of a pseudo random number generator and for calculating the attack success rate in a multiplier circuit protected by robust error-detecting codes.
10 citations
Cites methods from "Digital Systems Testing and Testabl..."
...In the following, we review the SAT and #SAT formalism and the formalism to model faults effects in circuits, before introducing the vulnerability analysis....
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27 Apr 1997
TL;DR: Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity.
Abstract: Despite all of the advantages that circular BIST offers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added to system paths. Result indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity.
10 citations