Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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22 Jun 2001
TL;DR: RFN, a formal property verification tool based on abstraction refinement, is developed to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results.
Abstract: We present RFN, a formal property verification tool based on abstraction refinement. Abstraction refinement is a strategy for property verification. It iteratively refines an abstract model to better approximate the behavior of the original design in the hope that the abstract model alone will provide enough evidence to prove or disprove the property.However, previous work on abstraction refinement was only demonstrated on designs with up to 500 registers. We developed RFN to verify real-world designs that may contain thousands of registers. RFN differs from the previous work in several ways. First, instead of relying on a single engine, RFN employs multiple formal verification engines, including a BDD-ATPG hybrid engine and a conventional BDD-based fixpoint engine, for finding error traces or proving properties on the abstract model. Second, RFN uses a novel two-phase process involving 3-valued simulation and sequential ATPG to determine how to refine the abstract model. Third, RFN avoids the weakness of other abstraction-refinement algorithms --- finding error traces on the original design, by utilizing the error trace of the abstract model to guide sequential ATPG to find an error trace on the original design.We implemented and applied a prototype of RFN to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results. On these designs, we successfully proved a few properties and discovered a design violation.
89 citations
Cites methods from "Digital Systems Testing and Testabl..."
...ATPG techniques [1] have been widely used for manufacturing tests....
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Patent•
23 Oct 2000
TL;DR: In this article, a hardware emulation system is described, which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board, and a method for dynamically testing the interconnect between integrated circuits is also disclosed.
Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.
89 citations
01 Nov 1997
TL;DR: Results show that the design team's custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models, was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.
Abstract: This paper describes the Design for Test (DFT) and silicon debug features of the Pentium(R) Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models. Results show that this approach was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.
89 citations
01 Jan 2005
TL;DR: A novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings is presented, and a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality are proposed.
Abstract: The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques. In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST. Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation. Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.
87 citations
01 Jan 2007
TL;DR: In this paper, a scheme for reducing power dissipation during test application, when scan test structure is used, is proposed, and algorithms required to exploit the proposed technique are discussed.
Abstract: Motivation for reducing power dissipation during test application is presented. A scheme for reducing power dissipation during test application, when scan test structure is used, is proposed. Algorithms required to exploit the proposed technique are discussed. Experimental results are presented. keywords: Power dissipation, Full Isolated Scan, Full Integrated Scan.
87 citations