Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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17 Oct 1993
TL;DR: This position paper provides a critical analysis of the different fault coverage measures used in practice, and their results may differ greatly.
Abstract: High fault coverage for single stuck faults (SSFs) is a necessary (but not sufficient) condition to achieve high defect coverage. The defect coverage of the manufacturing test is the main factor determining the quality of the products shipped to customers. Since the fault coverage for SSFs is a basic concept in testing, it should have a clear, well-understood, and universally accepted meaning. How can it be otherwise, when a minimum fault coverage is one of the requirements imposed on a design, when vendors make so many claims regarding the fault coverage obtained with their tools, when we apply DFT techniques to improve the fault coverage, and when almost every paper reports some fault coverage figures? In reality, there are several ways of computing the fault coverage, and their results may differ greatly. This position paper provides a critical analysis of the different fault coverage measures used in practice. >
10 citations
12 Nov 2003
TL;DR: In this article, a new ZBDD-based method is proposed to compactly store and efficiently search previously explored search-state for preimage computation, where both,solution and conflict subspaces are pruned based on simple set operations using ZBDDs.
Abstract: Computing image/preimage is a fundamental step in formal verification of hardware systems. Conventional OBDD-based methods for formal verification suffer from spatial explosion, since OBDDs can grow exponentially in large designs. On the other hand, SAT/ATPG based methods are less demanding on memory. But the run-time can be huge for these methods, since they must explore an exponential search space. In order to reduce this temporal explosion of SAT/ATPG based methods, efficient learning techniques are needed. In this paper, we present a new ZBDD based method to compactly store and efficiently search previously explored search-states for 'ATPG-based preimage computation'. We learn front these search-states and avoid searching their subsets or supersets. Both,solution and conflict subspaces are pruned based on simple set operations using ZBDDs. We integrate our techniques into an ATPG engine and demonstrate their efficiency on ISCAS '89 benchmark circuits. Experimental results show that significant search-space pruning for preimage computation is achieved, compared to previous methods.
10 citations
Dissertation•
15 May 2006
TL;DR: The results show that minimal test sets were generated for some benchmark circuits in CPU times that were almost half of what were required for an alternative dynamic compaction technique presented in the literature.
Abstract: Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or institutions and at their expense. The objective of this work is to find suitable targets for Automatic Test Pattern Generation (ATPG) such that a minimal test set is obtained for a combinational circuit. Original concepts of independence fault collapsing and concurrent test generation are developed and a novel test generation strategy based on these is devised. Independence fault collapsing groups faults into independent fault subsets such that each subset includes some faults that cannot be covered by the tests derived for any other subset. Using these fault subsets, optimally compact tests can be found. For an equivalence or dominance collapsed fault set an independence graph is generated using structural and functional independences. Each fault is represented as a node and an undirected edge between two nodes indicates independence of the corresponding faults; two independent faults cannot be detected by the same test vector. A " similarity-based " collapsing procedure reduces the graph to a fully-connected graph, whose nodes specify concurrently-testable fault targets for the ATPG. v Given a set of target faults, a concurrent test is an input vector that detects all (or most) faults in the set. These sets are obtained from the independence fault collapsing procedure. A new algorithm called the concurrent D algebra is presented for concurrent test generation. The independence fault collapsing algorithm and the concurrent D algebra together produced the minimal set of 12 tests for the 4-bit ALU (74181) circuit. But due to the complexity involved in generating the independence graph, this technique was not applied to the ISCAS85 benchmark circuits. A simulation based method was devised for generating the independence graph and for deriving concurrent tests using single-fault ATPG. The simulation based method was applied to the ISCAS85 combinational benchmark circuits. The results show that minimal test sets were generated for some benchmark circuits in CPU times that were almost half of what were required for an alternative dynamic compaction technique presented in the literature. vi Acknowledgments I would like to gratefully acknowledge the assistance, encouragement, support, patience and direction provided to me by my …
10 citations
03 Oct 2000
TL;DR: An end-to-end test methodology that utilizes BS architecture for testing boards and systems throughout the product life cycle is proposed and includes a programmable dynamic BS test architecture and a series of test modules that take advantage of the test architecture for complete fault coverage.
Abstract: ICs with IEEE 1149.1 boundary scan (BS) Architecture have been widely used in board level design to increase the testability. An end-to-end test methodology that utilizes BS architecture for testing boards and systems throughout the product life cycle is proposed. The proposed test methodology includes a programmable dynamic BS test architecture and a series of test modules that take advantage of the test architecture for complete fault coverage. Proposed design-for-testability (DFT) techniques guarantee the co-existence of BS resting with other system functions, such as in-system programming and DSP JTAG emulation. At board level, programmable dynamic scan chains are used in a divide-and-conquer fashion to increase the flexibility in the development phase (or design verification testing, DVT). Besides, since the DFT techniques are programmable they can be used as design-for-diagnosis to increase diagnosis resolution during DVT. Address scan port chips are used to enable multi-drop test bus architecture for backplane testing as well as system embedded testing. Other advanced techniques, such as analog subsystem testing and board-level built-in self-test, as well as how to re-use BS architecture in in-circuit testing and manufacture testing are also parts of the proposed methodology that takes advantage of BS architecture to provide full scale testing for systems.
10 citations
20 Nov 2009
TL;DR: The proposed model is fundamentally different from previous SAT-based ATPG models in that the number of used variables is significantly reduced, and allows significant performance improvements over other well-established models.
Abstract: Automatic Test Pattern Generation (ATPG) represents one of the first practical applications of Boolean Satisfiability (SAT). Even though ATPG can in general be considered easy for current state of the art SAT solvers, it is also the case that specific faults can be difficult to detect or prove undetectable, namely for large industrial circuits. Recent work on SAT-based ATPG has been motivated by industrial designs with ever increasing size, for which more efficient ATPG tools are essential. Moreover, ATPG models and algorithms find application in a number of other settings, that further motivate the development of more efficient SAT-based ATPG solutions. Interestingly, despite the potential interest of more efficient ATPG approaches, the core SAT-based ATPG model has remained essentially unchanged since it was first proposed in the late 80s. This paper proposes a new model for SAT-based ATPG. The proposed model is fundamentally different from previous SAT-based ATPG models in that the number of used variables is significantly reduced. Experimental results, obtained on a wide range of publicly available benchmarks, demonstrate that the new model allows significant performance improvements over other well-established models.
10 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Undetectable faults are often referred to as redundant, since undetectable faults are the result of redundancy in circuits [1]....
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...Automatic Test Pattern Generation (ATPG) is one of the most widely used approaches for identifying fabrication defects [1]....
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...Moreover, the single stuckat fault model (SSF) [1] is a typical model for representing defects, where a single connection in the circuit is assumed to be stuck at a given logic value....
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...In the SSF model a fault is represented by setting a single line in the circuit to be stuck at a given logic value, either 0 or 1....
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...One concrete example is that all the techniques, including static Unique Sensitization Points (USPs) [1], [8], learnt clause reuse and syntactic SAT [19], incremental CNF formula generation, and circuit-based static learning [23], that have been proposed over the years for SAT-based ATPG can be integrated with the new model....
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