Digital Systems Testing and Testable Design

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Digital Systems Testing and Testable Design

Miron Abramovici, M.A. Breuer, Arthur D. Friedman

01 Jan 1990-

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.

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Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.

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Proceedings Article•DOI•

Spectrum-based BIST in complex SOCs

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G. Kasturirangan¹, Michael S. Hsiao•Institutions (1)

Intel¹

28 Apr 2002

TL;DR: Experimental results for the spectral BIST showed that significantly more faults can be detected using spectral patterns than by conventional weighted random BIST technique.

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Abstract: Presents a spectral built-in-self-test (BIST) for a system-on-a-chip (SOC) environment. Test vectors are generated using the spectral properties of the embedded cores. Because some embedded cores may not have direct connections to the embedded TPG, it would be necessary to test them via other cores. As a result, testing such (cascaded) cores requires considerations on the spectral characteristics of the predecessor and successor cores. Matching spectral characteristics between the outputs of the predecessor core and dominant inputs of the successor core allows the successor core to be more testable. Experimental results for the spectral BIST showed that significantly more faults can be detected using spectral patterns than by conventional weighted random BIST technique.

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10 citations

Proceedings Article•DOI•

Logic BIST silicon debug and volume diagnosis methodology

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M. Enamul Amyeen¹, Andal Jayalakshmi¹, Srikanth Venkataraman¹, Sundar V. Pathy¹, Ewe C. Tan¹ - Show less +1 more•Institutions (1)

Intel¹

01 Sep 2011

TL;DR: A methodology for Logic BIST production fail volume diagnosis is developed and tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis are presented.

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Abstract: Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST production fail volume diagnosis and presented tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis. Results are presented showing successful isolation of silicon speed-paths on Intel® SOCs.

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10 citations

Cites background from "Digital Systems Testing and Testabl..."

...The true purpose of logic diagnosis is to determine the location of the defect though it can also be used to find the logic nature of the defect [5,6]....
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Proceedings Article•DOI•

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

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R. Inoue¹, Toshinori Hosokawa¹, Hideo Fujiwara²•Institutions (2)

Nihon University¹, Nara Institute of Science and Technology²

24 Nov 2008

TL;DR: This paper proposes a test generation method to detect specified fault models completely and to increase defect coverage as much as possible under test length constraint and gives experimental results for MCNC'91 benchmark circuits.

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Abstract: Since scan testing is not based on the function of the circuit, but rather its structure, scan testing is considered to be a form of over testing or under testing. It is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a test generation method to detect specified fault models completely and to increase defect coverage as much as possible under test length constraint. We give experimental results for MCNC'91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.

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10 citations

Cites background or methods from "Digital Systems Testing and Testabl..."

...(2) FSOD selects D-frontier[1, 2] to sensitize long fault propagation path segments....
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...Next, detection conditions for the main fault models such as bridging faults [2], transition faults [3], and path delay faults [3] are described....
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...Currently, scan testing for the stuck-at fault model [1, 2] is one of the most popular test methods for VLSIs....
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Proceedings Article•DOI•

Weighted pseudo-random BIST for n-detection of single stuck-at faults

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Chaowen Yu¹, Sudhakar M. Reddy¹, Irith Pomeranz²•Institutions (2)

University of Iowa¹, Purdue University²

15 Nov 2004

TL;DR: Experimental results show that the proposed test pattern generator achieves n-detection of single stuck-at faults with test set sizes growing linearly with n, and the hardware overhead grows modestly with n.

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Abstract: Detecting single stuck-at faults more than once has been shown to be an effective way to achieve high defect coverage. Recently it was observed that the number of tests required to achieve n-detection of single-stuck-at faults using pseudo-random sources may increase as n.logn with increasing values of n. In this paper, we investigate weighted pseudo-random BIST for n-detection of single stuck-at faults. We propose a hardware efficient weighted pseudo-random test pattern generator. Experimental results show that the proposed test pattern generator achieves n-detection of single stuck-at faults with test set sizes growing linearly with n. The hardware overhead grows modestly with n.

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10 citations

Cites methods from "Digital Systems Testing and Testabl..."

...The LFSR used in our work is a Type I LFSR [7] with the characteristic polynomial h(x) = x(24)+x(4)+x(3)+x+1....
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...Weighted random tests are commonly used to insure detection of random pattern resistant faults [7]....
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...For each circuit and each n, we collected experimental results for 10 runs of the procedure with different randomly selected initial states of the LFSR....
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...The LFSR used in our work is a Type I LFSR [7] with the characteristic polynomial h(x) = x24+x4+x3+x+1....
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...It consists of an LFSR, a phase shifter, several weight generator circuits, weight selection logic, inversion logic, several multiplexers, exclusive OR gates and some additional logic gates, and two counters (not shown in Proceedings of the 13th Asian Test Symposium (ATS 2004) 0-7695-2235-1/04 $20.00 © 2004 IEEE Figure 1)....
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Proceedings Article•DOI•

Multiple fault diagnosis with BDD based boolean differential equations

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Raimund Ubar, Jaan Raik, Sergei Kostin, Jaak Kousaar

11 Dec 2012

TL;DR: A novel 5-valued algebra is introduced for simplifying differential equations, and a discussion is presented how this approach can be used as a basis for hierarchical fault diagnosis to cope with the complexity problem.

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Abstract: We present a new idea for multiple fault diagnosis in combinational circuits, which combines the concept of multiple fault testing by test groups and solving Boolean differential equations by manipulation of Binary Decision Diagrams (BDDs). A novel 5-valued algebra is introduced for simplifying differential equations, and a discussion is presented how this approach can be used as a basis for hierarchical fault diagnosis to cope with the complexity problem.

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10 citations

Cites methods from "Digital Systems Testing and Testabl..."

...If a high defect coverage is desired it is obvious that to detect all logic faults, every detectable MSAF must be tested....
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...The tool of Boolean full differential should be used also for reasoning MSAF cases when some of the test groups will not pass....
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...In [4, 5] a conception of test groups was introduced, and the necessary conditions for detecting MSAF in combinational circuits were introduced....
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...Test pair concept is used to generate test patterns for MSAF by targeting SSAF as test generation objectives [2, 3]....
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...On the other hand, to use SSAF as test objectives raises a problem to avoid fault masking because of possible MSAF [1]....
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Digital Systems Testing and Testable Design

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Cites methods from "Digital Systems Testing and Testabl..."

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