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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Book ChapterDOI
01 Jan 1998
TL;DR: In this article, the authors proposed a method to test mixed analog-digital ICs using a built-in self-test (BIST) facility, which has been shown to reduce 50% of the manufacturing costs for some complex mixed-signal ICs.
Abstract: Electronics manufacturers are driven to produce new integrated circuits (IC’s) with higher quality in shorter production cycles (the well known time-to-market concept). In parallel, with the advent of submicron technologies digital circuits become more complex, with an increasing transistor-per-pin ratio making them hard-to-test without Design-For-Test (DFT) and Built-in Self-Test (BIST) facilities [1]. Also, during the past decade the production of mixed analog-digital IC’s have been dramatically developed due to the explosive growth of the multimedia and telecom markets and testing for quality assurance has proven to approach 50% of the manufacturing costs for some complex mixed-signal IC’s [2].

10 citations

Proceedings ArticleDOI
03 Dec 2015
TL;DR: A single set of tests based on functional description of CMOS cells that are more complex than primitive gates are derived, if applied, to detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell.
Abstract: In this paper we consider detection of faults in CMOS cells that are more complex than primitive gates. We derive a single set of tests based on functional description of the cells. The tests derived, if applied, detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell, in any implementation of the cell functions. We give results on an industrial design to demonstrate the benefits of the proposed tests relative to standard stuck-at, cell exhaustive and transition fault tests in covering faults in such cells.

10 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...It can be shown that test sets containing minimal true vertices and maximal false vertices of the function F realized by C detect all detectable AND, OR bridging [17] and 4-way bridging faults [18] between pairs of literals in F realized by C....

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  • ...A bridging fault at cell inputs may cause a feedback in the logic driving the cell and hence additional constraints on tests may be needed to avoid oscillations [17]....

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Proceedings Article
01 Jan 2010
TL;DR: The current work seeks to address this tradeoff between security, testability and test area overhead by presenting a challenge-response based Secure Test Wrapper structure, suitable for testing IP cores in a SoC environment.
Abstract: C ryptographic circuits need special test infrastructure due to the concern of security involved. Normal design for testability methods, such as scan chains, as applied to most ASICs cannot be applied directly to Cryptographic chips. These methods, though providing the highest testability, open backdoors or side-channels for attackers, to extract secret keys or Intellectual Property information from the core. Built-in Self-Test is normally applied for such secure chips, but it suffers from aliasing, high area overhead, and inadequate fault coverage, requiring additional deterministic top-up test patterns. Existing secure testing methods only provide security through obscurity by randomizing the scan chain operation. The current work seeks to address this tradeoff between security, testability and test area overhead by presenting a challenge-response based Secure Test Wrapper structure, suitable for testing IP cores in a SoC environment. This scheme includes the KATAN lightweight block-cipher into IEEE 1500 Standard Test Wrapper and as such provides an extremely compact locking and unlocking mechanism for the standard scan chains. The overhead to include this secure locking/unlocking mechanism is limited to about 9% compared to a standard scan and test wrapper. The main contributions of the paper are full testability, very high security and scalability of the proposed design.

10 citations

Proceedings ArticleDOI
31 Aug 2009
TL;DR: The proposed scheme makes unauthorized disclosure of valuable design almost infeasible, and can easily detect any alteration of the design file during transmission, and ensures authentication of the original designer as well as non-repudiation between the seller and the buyer.
Abstract: IP reuse is rapidly proliferating recent automated circuit design. It is facing serious challenges like forgery, theft and misappropriation of intellectual property (IP) of the design. Thus, protection of design IP is a matter of prime concern. In this paper, we propose a novel Internet-based scheme to tackle this problem. Input to the proposed scheme is a graph corresponding to a digital system design. Watermarking of the graph and its encryption are achieved using a new linear feedback shift register(LFSR)-based locking scheme. The proposed scheme makes unauthorized disclosure of valuable design almost infeasible, and can easily detect any alteration of the design file during transmission. It ensures authentication of the original designer as well as non-repudiation between the seller and the buyer. Empirical evidences on several benchmark problem sets are encouraging.

10 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...Let q(x) and Figure 1: A LFSR with a feedback loop r(x) be the quotient and remainder respectively obtained from the LF SR....

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  • ...3.1 Introducing LFSR De.nition 1....

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  • ...Some properties of LFSRs are as follows: Property 1: The number of 0s and 1s in an m-sequence obtained from an L-stage maximum-length LFSR are 2L−1 and 2L−1 − 1 respectively and thus, differs by only one [13]....

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  • ...Watermarking of the graph and its encryption are achieved using a new linear feedback shift register(LFSR)-based locking scheme....

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  • ...In the proposed scheme, the core concept involves en­cryption obtained by changing the interconnection patterns in the graph with the help of a LFSR [13]....

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Journal ArticleDOI
TL;DR: An efficient parallel scan test technique is introduced to minimize the test application time for the test patterns scheduled for concurrent scan test and Experimental results show that testing times are considerably reduced with little area overhead.
Abstract: Today’s System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

10 citations