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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Решение задачи прогнозирования экологического состояния города нейроэволюционныmи алгоритмами
TL;DR: A modified approach for artificial neural network ensembles is proposed, which is different from known before with combined application of existing schemes and methods for ensemble organization and it is shown that this approach allows increasing the accuracy of the resulting models.
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Hierarchical test generation for combinational circuits with real defects coverage
T. Cibakova,Maria Fischerova,Elena Gramatová,Wieslaw Kuzmicz,Witold A. Pleskacz,Jaan Raik,Raimund Ubar +6 more
TL;DR: A new parameter––probabilistic effectiveness of input patterns––has been used in the TPG technique with the goal of increasing real defect coverage and this parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits.
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High-Level Fault Modeling in Surface-Micromachined MEMS
N. Deb,R.D. Blanton +1 more
TL;DR: In this paper, the authors compared the results of schematic-level fault simulations with low-level finite element analysis (FEA) and demonstrated the efficacy of such an approach, achieving a 60X speedup over FEA with little accuracy loss in modeling defects caused by particles.
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Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams
J. P. Anita,P. Sudheesh +1 more
TL;DR: The primary objective of the proposed work is the generation of test patterns for a given set of multiple faults and the next objective is to reduce the test power which is the power consumed during testing.
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Multiple-seed TPG structures
TL;DR: A formula is established that shows how the seeds of any nonprimitive irreducible polynomial relate to each other, which leads to an efficient hardware implementation with small hardware overhead, irrespective of the number of seeds.