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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Book ChapterDOI
12 Infrastructure Intellectual Property for SoC Simulation and Diagnosis Service
TL;DR: The models and methods for creating Infrastructure Intellectual Property service for the functionalities System on Chip (SoC), which has a minimum set of the real time Built-In Self Test (BIST) tools, are proposed in this chapter.
Proceedings ArticleDOI
A methodology to reduce the computational cost of behavioral test pattern generation
TL;DR: In this article, the authors present different methods of computing testability measures for behavioral descriptions of digital circuits and integrate them into a behavioral deterministic test pattern generator to study the effectiveness of the proposed testability measure.
Proceedings ArticleDOI
Configurable spare processors: a new approach to system level fault-tolerance
TL;DR: This paper presents a new technique wherein several processors share one or more configurable spare processors, and addresses application bundling wherein n application control-data flow graphs are bundled into at most m groups such that the sum of the areas of the corresponding implementations is minimized.
Proceedings ArticleDOI
Efficient testability enhancement for combinational circuit
Y. Fang,A. Albicki +1 more
TL;DR: A novel testability enhancement scheme based on XOR Chain Structure is proposed, effective for improving both controllability and observability and incurred hardware overhead and performance penalty is relatively low.
Proceedings ArticleDOI
A current testing for CMOS logic circuits applying random patterns and monitoring dynamic power supply current
TL;DR: In this paper, a random current testing for CMOS logic circuits by monitoring a dynamic power supply current was discussed, where the outputs of a CUT are fed back to an LFSR.