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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
Citations
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Journal ArticleDOI
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
TL;DR: The proposed scheme relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter and outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.
Proceedings ArticleDOI
Physical planning with retiming
Jason Cong,Sung Kyu Lim +1 more
TL;DR: A unified approach to partitioning, floorplanning, and retiming for effective and efficient performance optimization is proposed and GEO obtains 35% and 23% better delay results while maintaining comparable cutsize, wirelength, and runtime results.
Proceedings ArticleDOI
Logic optimization by output phase assignment in dynamic logic synthesis
TL;DR: This paper presents this previously unaddressed problem of output phase assignment for minimum area duplication in dynamic logic synthesis and gives both optimal and heuristic algorithms for minimizing logic duplication.
Patent
Scan based testing of an integrated circuit for compliance with timing specifications
Grady L. Giles,Alfred L. Crouch,Odis Dale Amason,Matthew D. Pressly,Clark Shepard,M. Mateja,Lee Allen Corley,Daniel T. Marquette,Jason E. Doege +8 more
TL;DR: In this article, the authors propose a method and implementation for providing an improved testable design for an integrated circuit (IC) device, which includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit.
Proceedings ArticleDOI
A technique for logic fault diagnosis of interconnect open defects
TL;DR: The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect and diagnosis algorithms that leverage the diagnostic model while circumventing the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitance.