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Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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04 Dec 2000
TL;DR: An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power of multiple scan chain based circuits during testing.
Abstract: This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.
72 citations
01 Nov 1997
TL;DR: The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties.
Abstract: This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.
72 citations
03 Oct 2000
TL;DR: This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding, which has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.
Abstract: This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding. The proposed scheme requires a total of six test configurations and has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.
71 citations
TL;DR: The first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs) is presented.
Abstract: We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.
71 citations
Cites background from "Digital Systems Testing and Testabl..."
...Proof: Since any single faulty PLB is detected, a pair of faulty BUTs will escape detection only if they have a circular masking relation [ 32 ], where each faulty PLB masks the detection the other one....
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01 Jan 2000
TL;DR: The objective is to address test problems faced by the designer at the system level by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design.
Abstract: HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support ...
71 citations