Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented, and results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.
Abstract: A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust-hazard-free-test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS '89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms. >
70Â citations
TL;DR: Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease switching activity during BIST by significant amounts while providing high fault coverage.
Abstract: A new built-in self-test (BIST) test pattern generator (TPG) design, called low-transition random TPG (LT-RTPG), is presented. An LT-RTPG is composed of a linear feedback shift register (LFSR), a /spl kappa/-input AND gate, and a T flip-flop. When used to generate test patterns for test-per-scan BIST, it decreases the number of transitions that occur during scan shifting and, hence, decreases switching activity during testing. Various properties of LT-RTPGs are identified and a methodology for their design is presented. Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease switching activity during BIST by significant amounts while providing high fault coverage.
70Â citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Assume that the LFSR used by the LT-RTPG is external type, which is also called generator or type-I LFSR [1], [3]....
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...The internal type LFSR is also called divider or type-II LFSR [1], [3]....
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27 Sep 1993
TL;DR: Based on these characteristics, FPGA kernel architectures and related technologies are identified that will significantly improve the performance and capabilities of ASIC hardware emulators.
Abstract: The increasing complexity available in application-specific integrated circuits (ASICs) and the requirement for reduced design time have increased the importance of hardware emulators for ASIC system verification prior to first silicon. The authors review current ASIC hardware emulators based on field programmable gate arrays (FPGAs), including their limitations and constraints. Based on these characteristics, FPGA kernel architectures and related technologies are identified that will significantly improve the performance and capabilities of ASIC hardware emulators. >
70Â citations
Patent•
22 Nov 2010
TL;DR: In this paper, an integrated circuit including a first layer of logic circuits, and a second layer with logic circuits overlaying the first layer, where each flip-flop has at least one connection to the second layer, is described.
Abstract: An integrated circuit including a first layer of logic circuits, and a second layer of logic circuits overlaying the first layer, wherein the first layer includes a multiplicity of flip-flops wherein each of the flip-flops has at least one connection to the second layer, and wherein the second layer includes at least one logic circuit with inputs including the connection and with at least one output connected to the first layer.
70Â citations
03 Jan 1996
TL;DR: This paper proposes a novel approach to obtain a lower bound of the maximum power consumption using Automatic Test Generation (ATG) technique and shows that this approach generates the lower bound with the quality which cannot be achieved using simulation-based techniques.
Abstract: Excessive instantaneous power consumption in VLSI circuits may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is essential to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent input-pattern dependence of the problem, it is intractable to conduct an exhaustive search for circuits with a large number of primary inputs. Hence, the practical approach is to generate a tight lower bound and an upper bound for maximum power dissipation within a reasonable amount of CPU time. In this paper, instead of using the traditional simulation-based techniques, we propose a novel approach to obtain a lower bound of the maximum power consumption using Automatic Test Generation (ATG) technique. Experiments with MCNC and ISCAS-85 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulation-based techniques. In addition, a Monte Carlo based technique to estimate maximum power dissipation is described. It not only serves as a comparison version for our ATG approach, but also generates a metric to measure the quality of a lower bound from a statistical point of view.
70Â citations