Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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01 Oct 2007
TL;DR: This work presents a combinational scan compression method that preserves the low-impact advantages of traditional scan compression, while also allowing any number and distribution of Xs with virtually no loss of test quality.
Abstract: Traditional scan and, more recently, scan compression are increasingly accepted for reducing test cost and improving quality in ever more complex designs. Combinational scan compression techniques are attractive for their low impact on area, timing and design flow, but are best suited for designs with a limited number of unknowns (Xs). However, recent design performance and cost tradeoffs create a much higher density of Xs than previously expected. We present a combinational scan compression method that preserves the low-impact advantages, while also allowing any number and distribution of Xs with virtually no loss of test quality. Results on industrial designs with a varied density of Xs demonstrate consistent data and test time compressions with negligible impact on all design parameters.
63Â citations
Patent•
07 Oct 2004TL;DR: In this paper, various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed and computer readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of disclosed apparatus are also disclosed.
Abstract: Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.
62Â citations
30 Apr 1995
TL;DR: This work presents, for the first time, complete functional circuit models and tests for representative 74X-series and ISCAS-85 benchmark circuits, and applies the proposed methodology to them, demonstrating that functional testing can, with far less effort, produce test sets that provide complete coverage of SSL faults in practical circuits.
Abstract: A high-level fault modeling and testing philosophy is proposed which is aimed at ensuring full detection of low level, physical faults, as well as the industry-standard single stuck-line (SSL) faults. A set of independent functional faults and the corresponding functional tests are derived (induced) from the circuit under test; of particular interest are SSL-induced functional faults or SIFs. We present, for the first time, complete functional circuit models and tests for representative 74X-series and ISCAS-85 benchmark circuits, and apply the proposed methodology to them. These examples demonstrate that functional testing can, with far less effort than conventional method, produce test sets that provide complete coverage of SSL faults in practical circuits. Surprisingly, these test sets are also provably of minimal or near-minimal size.
61Â citations
TL;DR: An automatic test pattern generation (ATPG) technique is proposed that reduces switching activity during testing of sequential circuits that have full scan to permit safe and inexpensive testing of low-power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speed.
Abstract: An automatic test pattern generation (ATPG) technique is proposed that reduces switching activity during testing of sequential circuits that have full scan. The objective is to permit safe and inexpensive testing of low-power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speed. The approach works with standard scan designs that are commonly used and typically have significantly lower overhead than enhanced scan designs. The proposed ATPG exploits all possible "don't cares" that occur during scan shifting, test application, and response capture to minimize switching activity in the circuit under test. An ATPG that minimizes the number of state inputs that are assigned specific binary values has been developed. Don't cares at state inputs are assigned binary values that cause the minimum number of transitions during scan shifting and don't cares at primary inputs during scan shifting and capture are used to block gates that may have transitions during scan shifting. The proposed technique has been implemented and the generated tests are compared with those generated by a simple PODEM implementation for full scan versions of ISCAS89 benchmark circuits.
61Â citations
Cites background from "Digital Systems Testing and Testabl..."
...If the inversion parity of a path is 1, then the path is said to have odd inversion parity; otherwise, the path is said to have even inversion parity[ 11 ]....
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07 Nov 1993
TL;DR: A method for high level synthesis with testability is presented with the objective to generate self-testable RTL datapath structures based on a new improved testability model that generates various testable design styles while reducing the circuit sequential depth from controllable to observable registers.
Abstract: A method for high level synthesis with testability is presented with the objective to generate self-testable RTL datapath structures. We base our approach on a new improved testability model that generates various testable design styles while reducing the circuit sequential depth from controllable to observable registers. We follow the allocation method with an automatic test point selection algorithm and with an interactive tradeoff scheme which trades design area and delay with test quality. The method has been implemented and design comparisons are reported.
60Â citations