Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: A new structural testing of phase-locked loops (PLLs) using charge-based frequency measurement BIST (CF-BIST) technique, which performs simple dc-like charge injection tests, suitable for high-speed PLL applications.
Abstract: We propose a new structural testing of phase-locked loops (PLLs) using charge-based frequency measurement BIST (CF-BIST) technique. The technique uses the existing charge-pump as the stimulus generator and the VCO/divide-by-N as the measuring device to reduce the area overhead. This approach performs simple dc-like charge injection tests, thus, it is suitable for high-speed PLL applications. Fault simulation results show higher fault coverage than a previous test method with less die area. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST structure for a PLL is possible.
55 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Although BIST for digital integrated circuits (ICs) is widely used [ 2 ], manufacturers of mixed-signal IC’s are still searching for an appropriate BIST solution [3]‐[8]....
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25 Apr 1994
TL;DR: The authors state and formally prove results regarding the types of faults identified as undetectable and/or redundant by existing test generation procedures and by procedures proposed specifically for this purpose.
Abstract: Considers undetectable and redundant faults in synchronous sequential circuits. The authors state and formally prove results regarding the types of faults identified as undetectable and/or redundant by existing test generation procedures and by procedures proposed specifically for this purpose. They distinguish between procedures that identify undetectable faults and procedures that identify redundant faults. They also give a detailed characterization of the types of faults that can be classified by each procedure considered and the types of faults that cannot be classified. The authors present examples and experimental evidence of these limitations. >
54 citations
24 Jun 1990
TL;DR: This paper applies recently developed necessary and sufficient conditions for robust path-delay-fault testability to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability.
Abstract: In this paper we apply recently developed necessary and sufficient conditions for robust path-delay-fault testability to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. For circuits which can be flattened to two levels, we give a covering procedure which optimizes for robust path delay fault testability. These two-level circuits can then be algebraically factored to produce robustly path-delay-fault testable multilevel circuits. For regular structures which cannot be flattened to two levels, we give a composition procedure which allows for the construction of robustly path-delay-fault testable regular structures. Finally, we show how these two techniques can be combined to produce cascaded combinational logic blocks that are robustly path-delay-fault testable. We demonstrate these techniques on a variety of examples. It is possible to produce entire chips that are fully path delay testable using these techniques.
54 citations
TL;DR: Special emphasis is put on deterministic BIST methods as they do not require any modifications of the core under test and help to protect intellectual property (IP).
54 citations
26 Apr 1999
TL;DR: Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds, especially if the test set contains many don't-cares.
Abstract: We present a new approach for built-in pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the TGC and the CUT; it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds, especially if the test set contains many don't-cares.
54 citations
Cites methods from "Digital Systems Testing and Testabl..."
...TRCs have recently been proposed for the design of scalable TGCs for high-speed datapath circuits, and to generate pseudoexhaustive test patterns for random-access memory (RAM) testing [3, 10]....
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...This can be easily achieved by following the BILBO technique of reconfiguring scan registers as TGCs [1]; it thus obviates the need for an external TGC....
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...We combine TRC-based TGCs with width compression by first encoding the columns inTD, and then applying the seed selection approach to the width-compressed test set....
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...TGCs with test-width compression....
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...TGCs for register-based designs....
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