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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
A security protocol for sensor networks
TL;DR: A new security protocol especially suited for sensor networks, which uses a novel encryption method for secure message transmission and results performed on a network simulator are presented.
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A practical current sensing technique for I/sub DDQ/ testing
TL;DR: This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT) and can be used to monitor the current-related faults of both CMOS and non-CMOS circuits.
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Multiple error detection and identification via signature analysis
TL;DR: This paper shows how signature analysis can be used not only for fault detection but also for identification of multiple errors produced by faults in the circuits under test and extends the use of BCH codes for error detection and correction to include nonprimitive polynomials.
A self-repairing multiplexer-based FPGA inspired by biological processes
TL;DR: These Ecole polytechnique federale de Lausanne EPFL thesis 1827 are presented as a curriculum vitae for the summer term of 1998.
Proceedings ArticleDOI
Digital sensitivity: predicting signal interaction using functional analysis
TL;DR: It is found that it is possible to predict signal interaction by signal functionality alone, leading to a significant amount of robust switching isolation, independent of parasitics introduced by layout or semiconductor process.