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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Proceedings ArticleDOI
K. Scott1, K. Keutzer1
01 May 1994
TL;DR: It is found that relatively simple modifications in a cell library can lead to 20-30% improvements in final circuit speed, and that the principles motivating these modifications are not embodied in the cell sets of most commercial ASIC libraries.
Abstract: This paper examines the issues associated with building a cell library that will serve as the target for an automated synthesis tool and particularly focuses on cell library modifications that will improve the speed of a circuit. A number of library modifications are suggested here, and an experimental method for evaluating their effectiveness is described. This method is then used to quantify the importance of each modification as clearly as possible. The conclusion of this work is that relatively simple modifications in a cell library can lead to 20-30% improvements in final circuit speed, and that the principles motivating these modifications are not embodied in the cell sets of most commercial ASIC libraries. >

53 citations

Proceedings ArticleDOI
10 Jun 2002
TL;DR: An interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hard¿ware overhead is proposed.
Abstract: Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hardware overhead. Tester fail-data collection is based on a novel construct incorporated into the design-extensions of the standard test interface language (STIL). The implementation of the proposed method is presented and analyzed.

52 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...Design-for-test (DFT) methods to reduce test cost include scan ([2], [3]) and, increasingly, BIST [4], [5]....

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Journal ArticleDOI
TL;DR: A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/ outputs of the realization are given.
Abstract: A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/outputs of the realization are given. Since ESOP is the most general form of AND-EXOR representations, our realization and test set are more versatile than those described by other researchers for the restricted GRM, FPRM, and PPRM forms of AND-EXOR circuits. Our circuit realization requires only two extra inputs for controllability and one extra output for observability. The cardinality of our test set for an n input circuit is (n+6). For Built-in Self-Test (BIST) applications, we show that our test set can be generated internally as easily as a pseudorandom pattern and that it provides 100 percent single stuck-at fault coverage. In addition, our test set requires a much shorter test cycle than a comparable pseudoexhaustive or pseudorandom test set.

52 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...Th e results from the applied test vectors are collected from the function outputf and from the extra observable outputs o1 ando2; then compressed in the signature register, which can simply be an LFSR based Multiple Input Signature Register (MISR) [1]....

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  • ...The large increase in the complexity of ASICs has led to a much greater need for circuit testability and Built-In-Sel f-Test (BIST) [1]....

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01 Jan 2005
TL;DR: A survey of the recent advances in this field can be found in this paper, where several test strategies and algorithms in test architecture design and optimisation, test scheduling and test resource partitioning have emerged to tackle the resource-constrained core-based system-on-a-chip test.
Abstract: Manufacturing test is a key step in the implementation flow of modern integrated electronic products. It certifies the product quality, accelerates yield learning and influences the final cost of the device. With the ongoing shift towards the core-based system-on-a-chip (SOC) design paradigm, unique test challenges, such as test access and test reuse, are confronted. In addition, when addressing these new challenges, the SOC designers must consciously use the resources at hand, while keeping the testing time and volume of test data under control. Consequently, numerous test strategies and algorithms in test architecture design and optimisation, test scheduling and test resource partitioning have emerged to tackle the resource-constrained core-based SOC test. This paper presents a survey of the recent advances in this field.

52 citations

Proceedings ArticleDOI
09 Nov 2003
TL;DR: The design and implementation of SATORI is described - a fast sequential justification engine based on state-of-the-art SAT and ATPG techniques that enables bothbinational and sequential back-jumping and conflict-based and illegal state learning across time-frames.
Abstract: We describe the design and implementation of SATORI-a fast sequential justification engine based on state-of-the-art SAT and ATPG techniques. We present several novel techniques that propel SATORI to a demonstrable 10x improvement over a commercial engine. Traditional sequential justification based on ATPG or, on a bounded model of the sequential circuit using SAT, has diverging strengths and weaknesses. In this paper, we contrast these techniques and describe how their-strengths are combined in SATORI. We use conflict-based learning in each time-frame and illegal state learning across time-frames. This enables both combinational and sequential back-jumping. We experimentally analyze the main features of SATORI by comparing SATORI'S performance against a state-of-the-art SAT solver-ZCHAFF using a bounded model, and a commercial sequential ATPG engine performing justification. Additional results are presented for SATORI versus the commercial ATPG engine and VIS on ISCAS '89 and ITC'99 benchmark circuits for an application to assertion checking.

52 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...ATPG is used primarily for manufacturing-fault test-vector generation, but has found applications in logic synthesis and bounded model checking [3, 12]....

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