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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Patent
Combinational test pattern generation method and apparatus
TL;DR: In this paper, a change input scan chain test pattern is coupled with an initialization scan-chain test pattern such that a resultant scanchain test patterns is produced and applied to at least one combinational logic path.
Journal ArticleDOI
Reduction of power consumption in scan-based circuits during test application by an input control technique
Tsung-Chu Huang,Kuen-Jong Lee +1 more
TL;DR: A D-algorithm-like CP generator is developed to generate an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be reduced or even eliminated.
Journal ArticleDOI
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
TL;DR: A new comparator design featuring wide-range and high-speed operation using only conventional digital CMOS cells and a regular reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth.
Proceedings ArticleDOI
Combinational ATPG theorems for identifying untestable faults in sequential circuits
TL;DR: In this paper, the authors present two theorems for identifying untestable faults in sequential circuits, single-fault theorem and multi-factored theorem, which states that if a single fault in a combinational array is untastable then that fault is untested in the sequential circuit.
Proceedings ArticleDOI
A novel SAT all-solutions solver for efficient preimage computation
TL;DR: A novel all-solutions preimage SAT solver with a new success-driven learning algorithm employing smaller cut sets, a marked CNF database non-trivially combining success/conflict- driven learning, and a practical method of storing all solutions into a canonical OBDD format.