Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
More filters
17 Oct 1993
TL;DR: This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST, and shows that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage.
Abstract: This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths such that some of the BIST and scan logic is shared with the functional logic. Logic sharing is possible when scan dependence is introduced in the design. Other BIST design techniques attempt to avoid scan dependence because it can reduce the fault coverage of embedded, multiple input signature registers (MISRs). We show that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage. We present our results for benchmark circuits that have been synthesized to take advantage of scan dependence in a circular BIST architecture. >
48 citations
25 Jun 1991
TL;DR: The test generation problem for synchronous sequential circuits is considered in the case where hardware reset is not available, and the use of multiple fault free responses as well as multiple time units for fault detection is suggested.
Abstract: The test generation problem for synchronous sequential circuits is considered in the case where hardware reset is not available. The observations which form the motivation for the work are given. On the basis of the observations, the use of multiple fault free responses as well as multiple time units for fault detection is suggested. Application to gate level synchronous sequential circuits is then considered. Experimental results are given to support the claim that a small number of observation times is required, and that a small number of fault free responses need be stored for every fault. 100% fault efficiency is achieved. >
48 citations
10 Mar 2008
TL;DR: A mutation model for perturbing transaction level modeling (TLM) SystemC descriptions is proposed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.
Abstract: Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.
48 citations
Additional excerpts
...In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions....
[...]
Patent•
07 Nov 2010
TL;DR: In this paper, a semiconductor device comprising first layer comprising multiplicity of first transistors and second layer consisting multiplicityof second transistors is defined, and at least one function constructed by the first transistor is structure so it could be replaced by a function created by the second transistor.
Abstract: A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.
48 citations
01 Jan 1998
TL;DR: IDDQ Testing is a well accepted testing approach based on the observation of the quiescent current consumption but its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.
Abstract: I DDQ Testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which escape other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.
48 citations