Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
More filters
01 Jun 2000
TL;DR: This paper presents an algorithm for generating test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level using a data structure named assignment decision diagram.
Abstract: In this paper, we present an algorithm for generating test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. To do this we utilize a data structure named assignment decision diagram which has been proposed previously in the field of high level synthesis. The advent of RTL synthesis tools have made functional RTL designs widely popular. This paper addresses the problem of test pattern generation directly at this level due to a number of advantages inherent at the RTL. Since the number of primitive elements at the RTL is usually lesser than the logic level, the problem size is reduced leading to a reduction in the test generation time over logic-level ATPG. A reduction in the number of backtracks can lead to improved fault coverage and reduced test application time over logic-level techniques. The test patterns thus generated can also be used to perform RTL-RTL and RTL-logic validation. The algorithm is very versatile and can tackle almost any type of single-clock design though performance varies according to the design style. It gracefully degrades to an inefficient logic-level ATPG algorithm if it is applied to a logic-level circuit. Experimental results demonstrate that over 1000 times reduction in test generation time can be achieved by this algorithm on certain types of RTL circuits without any compromise in fault coverage.
46 citations
Cites methods from "Digital Systems Testing and Testabl..."
...The algorithm can be .ne tuned to generate greater fault coverage at the expense of CPU time much like logic-level sequential ATPG....
[...]
...This is very similar to logic-level ATPG....
[...]
...The classical ATPG methods target the problem at the logic level and might require large amounts of computing time and resources to generate tests of even moderately sized sequential circuits [1]....
[...]
...The algorithm gracefully degrades to an inef.cient logic-level ATPG algorithm if given a functional RTL circuit that is pure Boolean in nature....
[...]
...In case of a single-bit value, it signi.es the 1/0 fault i.e. the good value on the variable should be 1 and the faulty value 0 (it is the same as D in the D-algorithm used in logic-level ATPG [1])....
[...]
Patent•
10 Aug 2012
TL;DR: In this paper, a first layer of first transistors is overlaid by at least one interconnection layer, wherein the interconnection layers includes metals such as copper or aluminum; a second layer including second transistors, the second layer is less than about 0.4 micron thick.
Abstract: A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.
46 citations
07 Jun 2004
TL;DR: A novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead is introduced.
Abstract: X-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead. XDBIST test-coverage, full X-tolerance and scan-based diagnosis ability are preserved and are the same as deterministic scan-ATPG.
46 citations
Cites methods from "Digital Systems Testing and Testabl..."
...X-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture....
[...]
10 Nov 2002
TL;DR: This survey outlines basic SAT- and ATPG- procedures as well as their applications in formal hardware verification and attempts to give the reader a trace trough literature and provide a basic orientation concerning the problem formulations and known approaches.
Abstract: In this survey, we outline basic SAT- and ATPG- procedures as well as their applications in formal hardware verification We attempt to give the reader a trace trough literature and provide a basic orientation concerning the problem formulations and known approaches in this active field of research
46 citations
TL;DR: It is shown that circuits that have synchronizing sequences have certain properties that help in identifying logic that can be removed, and the class of removable lines is extended beyond those corresponding to redundant faults to include some partially detectable faults as well.
Abstract: We consider the removal of redundant logic from synchronous sequential circuits that have synchronizing sequences. The logic to be removed is identified by determining line stuck-at faults that do not affect the operation of the circuit. Such signal lines and some of the logic surrounding them can be removed without affecting the operation of the circuit. We show that circuits that have synchronizing sequences have certain properties that help in identifying logic that can be removed. Specifically, their state diagrams have a strongly connected component that contains all the synchronization states. This strongly connected component, called the main strongly-connected component, is reachable from all other strongly connected components. In addition to redundant faults that can always be removed, we show that there are two types of partially detectable faults in circuits that have synchronizing sequences. In the presence of the first type of faults, the circuit becomes unsynchronizable. Signal lines carrying such faults cannot be removed. The other type of partially detectable faults leave the circuit synchronizable. We show that such faults do not affect the main strongly connected component, and hence the corresponding signal lines can be removed without affecting the operation of the circuit after it is synchronized. We also define weakly synchronizable circuits acid derive similar results regarding the removal of redundant logic in them. The class of removable lines is thus extended beyond those corresponding to redundant faults to include some partially detectable faults as well. We present experimental evidence to the existence of partially detectable faults that correspond to signal lines that can be removed in benchmark circuits.
46 citations