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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
TL;DR: This paper proposes a correction technique for simulation-based ATPG based on identifying the diverging state and on computing a fault cluster (faults close to each other) which has been used to generate tests with very high fault coverage.
Proceedings ArticleDOI
Algorithms for solving Boolean satisfiability in combinational circuits
TL;DR: This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits and provides clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
Proceedings ArticleDOI
Serial fault emulation
TL;DR: Experimental results indicate that SFE should be two orders of magnitude faster than sofware approaches for designs containing more than 100000 gates.
Proceedings ArticleDOI
Random pattern testing for sequential circuits revisited
TL;DR: The algorithm consists of simulating a sequential circuit systematically, possibly with partial scan, in conjunction with the hold method, and is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan.
Journal ArticleDOI
Testing of core-based systems-on-a-chip
TL;DR: A comprehensive framework that generates low-overhead compact test solutions for SOCs and introduces finite-state automata (FSA) for modeling tests, transparency modes, and testing hardware behavior is provided.