Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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07 Jun 2004
TL;DR: It is described how DPLL search can be modified by using efficient finite-domain constraint propagation to improve communication between interacting integer and Boolean domains, which enables efficient combination of Boolean SAT and linear integer arithmetic solving techniques.
Abstract: We present a novel hybrid finite-domain constraint solving engine for RTL circuits, that automatically uses data-path abstraction. We describe how DPLL search can be modified by using efficient finite-domain constraint propagation to improve communication between interacting integer and Boolean domains. This enables efficient combination of Boolean SAT and linear integer arithmetic solving techniques. We use conflict-based learning using the variables on the boundary of control and data-path for additional performance benefits. Finally, the hybrid constraint solver is experimentally analyzed using some example circuits.
45 citations
Cites background from "Digital Systems Testing and Testabl..."
...Numerouselectronic design automation(EDA) problems can be efficiently represented by a combination of Boolean and integer constraints – like formal verification and functional test generation for RTL circuits....
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30 Oct 2001
TL;DR: A BIST-based test methodology is presented that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips.
Abstract: Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. We present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips.
45 citations
TL;DR: Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters.
Abstract: In this paper, a new method for the design of unidirectional combinational circuits is proposed Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code All single stuck-at faults are detected by the method proposed
45 citations
Cites methods from "Digital Systems Testing and Testabl..."
...The existence of a redundant fault can be used further to simplicity the circuit fu by redundancy elimination as described in [22], for example....
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01 Jun 1999
TL;DR: In this article, the authors propose a test generation approach for design verification of pipelined microprocessors based on a "pipeframe" organization that exploits high-level knowledge about the operation of pipelines.
Abstract: This paper addresses test generation for design verification of pipelined microprocessors. To handle the complexity of these designs, our algorithm integrates high-level treatment of the datapath with low-level treatment of the controller and employs a novel "pipeframe" organization that exploits high-level knowledge about the operation of pipelines. We have implemented the proposed algorithm and used it to generate verification tests for design errors in a representative pipelined microprocessor.
45 citations
20 Oct 1996
TL;DR: T TOPS, Stanford CRC's synthesis-for-test tool, has been modified to implement orthogonal scan paths for synthesized circuits, which have roughly half the overhead of traditional scan paths and greatly reduce the test application time.
Abstract: Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead-area, delay and test application time by sharing functional and test logic. Orthogonal scan paths are orthogonal to traditional scan paths. Judicious ordering of the registers in the orthogonal scan path can allow the scan path to be implemented entirely with existing interconnect, resulting in no additional wiring to connect the scan path and no performance degradation due to additional loading on the bistable outputs. Taking the orthogonal scan path into account during high-level synthesis operations such as register allocation allows for a better final solution, but orthogonal scan paths can also be used with non-synthesized data path. Orthogonal scan paths have roughly half the overhead of traditional scan paths and greatly reduce the test application time. TOPS, Stanford CRC's synthesis-for-test tool, has been modified to implement orthogonal scan paths for synthesized circuits.
45 citations