Digital Systems Testing and Testable Design
Citations
44 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...6 Experimental Results The success-driven learning algorithm together with a basic PODEM and two ATPG enhancements (improved backtrace with con.ict check [12], con.ict analysis [11]) were implemented in 5,000 lines of C code....
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...Search State Equivalence. is.ed), backtrace to PIs along all the X-paths in its fanin cone; 2. record every speci.ed input to all unspeci.ed gate-output encountered in this depth-.rst search (in our example, there is er=eonly one X-path z--, 1is the speci.ed input of the eOeunspeci.ed gate and 0is the one for unspeci.ed gate z.); reP 3. record the unspeci.ed PIs at the end of each X-Path ( in the example)....
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...Notice that unlike conventional PODEM which returns either SUC-CESS or FAIL, this function does not have a return value because we always enforce a backtrack when a solution is found so that it can continue to search for the next solution....
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...The function eL()is a standard function in ATPG that uses controllability and observability as heuristics to .nd next decision PIs through backtracing along X-paths [1]....
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...A naive way of using PODEM to compute preimages is to enforce a backtrack whenever a solution is found so that the algorithm could continue to search for the next solution until the entire search space is implicitly enumerated....
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43 citations
Cites background from "Digital Systems Testing and Testabl..."
...Logic diagnosis tools today [1][2][3][4][5][13][18] can determine the most likely location inside a failing die from which the failures originate....
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43 citations
43 citations
Cites background or methods or result from "Digital Systems Testing and Testabl..."
...For fault detection, test compaction must be done such that the signature of the fault-free response is different from the signature of any modeled fault, otherwise, some loss of fault coverage occurs due to aliasing [ 1 ]....
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...For fault detection, several methods to compact test data into a signature have been proposed earlier [ 1 ]....
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...In the case where the response of the circuit cannot be explained by any of the modeled faults, the fault best matching the observed response is selected, and the fault is assumed to occur at the same location [ 1 ], [2], [3], [4], [5], [6], [7], [8]....
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...The problem of fault location at the chip level has been considered in numerous works [ 1 ], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19]....
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...Previous works can be found in [ 1 ], [2], [3], [6]....
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43 citations
Cites methods from "Digital Systems Testing and Testabl..."
...The algorithm follows a similar process as the D-algorithm [8] originally proposed for ATPG and utilizes 3-value simulation....
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...The two # columns show the numbers after state reduction with modi.ed D-algorithm (step 1) and then, with three value simulation (step 2), respectively....
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...This approach is based on the assumption that the D-algorithm can usually .nd a solution containing much fewer assignments than that of a SAT solver....
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...Hence, the D-algorithm is used as a trace procedure, not as a search procedure....
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...From the results, we can see that the modi.ed D-algorithm could reduce most of the unnecessary assignments to the state variables, so the number of 3-value simulation runs can be greatly reduced....
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