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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Patent
Method of constructing a semiconductor device and structure
TL;DR: In this article, the authors proposed a method of manufacturing a semiconductor device, which includes, providing a first monocrystalline layer including semiconductor regions, overlaying the first layer with an isolation layer, transferring a second layer comprising semiconductor region to overlay the isolation layer and subsequently etching the second layer as part of forming at least one transistor.
Proceedings ArticleDOI
A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system
TL;DR: A low power 128-bit LFSR for efficient use in portable Bluetooth telecommunication systems is proposed and two methods to reduce the conventional L FSR switching activity are introduced.
Proceedings ArticleDOI
Independent test sequence compaction through integer programming
Petros Drineas,Yiorgos Makris +1 more
TL;DR: This work formulation of the compaction of independent test sequences for sequential circuits as an integer program yields the first polynomial time approximation algorithm for this problem, which provides a provably good approximation guarantee while running in time polynometric with respect to the number of vectors.
Proceedings ArticleDOI
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
TL;DR: The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power and include a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.
Journal ArticleDOI
Dynamic state traversal for sequential circuit test generation
TL;DR: A new method for state justification is proposed for sequential circuit test generation, using the linear list of states dynamically obtained during the derivation of test vectors to guide the search during state justification.