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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Fault collapsing via functional dominance
TL;DR: A graph-theoretic hierarchical fault collapsing method from the recent literature can then collapse faults in any large cell-based circuit and it is found that the size of the dominance collapsed set for an exclusive-OR cell reduces to just four faults when functional dominance is considered.
Proceedings ArticleDOI
Fault Dictionary Based Scan Chain Failure Diagnosis
TL;DR: In this paper, a fault dictionary based scan chain failure diagnosis technique is presented, which is up to 130 times faster with the same level of diagnosis accuracy and resolution compared with fault simulation based diagnosis technique.
Proceedings ArticleDOI
Adaptive techniques for improving delay fault diagnosis
J. Ghosh-Dastidar,Nur A. Touba +1 more
TL;DR: Experimental results are shown indicating that the number of suspects can be reduced dramatically for both single and multiple delay faults, and two new techniques based on adjacency testing and delay-size bounding are presented.
Journal ArticleDOI
On the properties of the input pattern fault model
R.D. Blanton,John P. Hayes +1 more
TL;DR: The IP fault model is described and a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools is provided to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder.
Journal ArticleDOI
Modeling and Mitigating Transient Errors in Logic Circuits
TL;DR: A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic.