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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Journal ArticleDOI
TL;DR: A novel application of the Gauss-elimination procedure is proposed to find the seeds as well as the polynomials in a general programmable LFSR to offer multiple-seed and multiple-polynomial PRPG for IC testing.
Abstract: This paper presents a new and efficient strategy of pseudorandom pattern generation (PRPG) for IC testing. It uses a general programmable LFSR (P-LFSR) to offer multiple-seed and multiple-polynomial PRPG. The deterministic pattern set generated by an ATPG tool or supplied by the designers is used to guide the generation of pseudorandom patterns. A novel application of the Gauss-elimination procedure is proposed to find the seeds as well as the polynomials. With an intelligent heuristic to further utilize the essential faults, this approach becomes very efficient, even for the random pattern resistant (RPR) circuits. Experiments are conducted on the ISCAS-85 benchmarks and the full scan version of the ISCAS-89 benchmarks. For all benchmark circuits, complete fault coverage is achieved with good balance on the hardware overhead and the test lengths as compared to other schemes.

41 citations

Proceedings ArticleDOI
30 Apr 1995
TL;DR: It is demonstrated that using traditional methods the probability of detecting nontarget defects drops rapidly as the fault coverage approaches 100% and the mechanism which produces this effect is explained and a new test pattern generation approach is described with better testing efficiency.
Abstract: Testing is an indispensable process to weed out the defective parts coming out of the manufacturing process. Traditionally, test generation targets on a specific fault model, usually the single stuck-at fault model, to produce tests that are expected to identify defects such as unintended shorts and opens. With this approach, the test quality relies on fortuitous detection of the non-target defects. As the quality demands and circuit sizes increase, the feasibility of test generation on a single fault model becomes questionable. In the paper, we present empirical data from experiments on ISCAS benchmark circuits to demonstrate that using traditional methods the probability of detecting nontarget defects drops rapidly as the fault coverage approaches 100%. By assuming surrogates, we explain the mechanism which produces this effect and describe a new test pattern generation approach with better testing efficiency.

41 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...Many improvements on uniformly random testing are possible and can be found in [ABRSO]....

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  • ...Other popular fault models include bridging faults, transition faults (gate delay faults), path delay faults, functional faults, etc [ABRSO]....

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  • ...In this example, we consider a reduced check point fault set (see [ABRSO]) which consists of six stuck-at faults (SAF), AO,Al,Bl,CO,Cl,Dl...

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Proceedings ArticleDOI
13 Nov 1997
TL;DR: This work would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays.
Abstract: Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. However, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulation is expensive. Thus, we would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays. Results for four delay models are reported for the ISCAS85 combinational benchmark circuits, ISCAS89 sequential benchmark circuits, and several synthesized circuits.

41 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...Parallel-pattern simulation [ 19 ] is used to speed up the process in which 32 candidate sequences from the population are simulated simultaneously, with values bit-packed into 32-bit words....

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Journal ArticleDOI
TL;DR: This work presents an attempt to draw inspiration from biology in the design of a novel digital circuit: a field-programmable gate array (FPGA), endowed with two features motivated and guided by the behavior of biological systems: self-replication and self-repair.
Abstract: Biological organisms are among the most intricate structures known to man, exhibiting highly complex behavior through the massively parallel cooperation of numerous relatively simple elements, the cells. As the development of computing systems approaches levels of complexity such that their synthesis begins to push the limits of human intelligence, engineers are starting to seek inspiration in nature for the design of computing systems, both at the software and at hardware levels. We present one such endeavor, notably an attempt to draw inspiration from biology in the design of a novel digital circuit: a field-programmable gate array (FPGA). This reconfigurable logic circuit will be endowed with two features motivated and guided by the behavior of biological systems: self-replication and self-repair.

41 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...1 Self-Test in MuxTree Any literature search, however superficial, on the subject of testing will reveal the existence of a considerable variety of approaches to implementing self-test in digital circuits [1], including some that can be applied to FPGAs [2, 13, 30]....

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Journal ArticleDOI
TL;DR: It is shown that many parameter faults are undetectable irrespective of which test methodology is being used to catch them, and the small-size parameter fault coverage is defined, and ways to calculate or estimate it are described.
Abstract: This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits and sheds new light on a number of very important test attributes. We show that there are inherent limitations with regard to analog faults detectability. It is shown that many parameter faults are undetectable irrespective of which test methodology is being used to catch them. It is also shown that, in many cases, the detectable minimum-size parameter fault is considerably larger than the normal parameter drift. Sometimes the minimum-size detectable fault is two to five times the parameter drift. We show that one of the fault-masking conditions in analog circuits, commonly believed to be true, is, in fact, untrue. We illustrate this with a simple counter example. We also show that, in analog circuits, it is possible for a fault-free parameter to mask an otherwise detectable parametric fault. We define the small-size parameter fault coverage, and describe ways to calculate or estimate it. This figure of merit is especially suitable in characterizing the test efficiency in the presence of small-size parameter faults. We further show that circuit specification requirements may be translated into parameter tolerance requirements. By doing so, a test for parametric faults can, indirectly, address circuit specification compliance. The test limitations of parametric faults in analog circuits are illustrated using numerous examples.

41 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...Digital test methodology has been resting on a relatively solid ground in both theory and practice [ 1 ], [2]....

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  • ...This is a well-known phenomenon in the digital test domain [ 1 ], [2]....

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