Digital Systems Testing and Testable Design
Citations
41 citations
41 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Many improvements on uniformly random testing are possible and can be found in [ABRSO]....
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...Other popular fault models include bridging faults, transition faults (gate delay faults), path delay faults, functional faults, etc [ABRSO]....
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...In this example, we consider a reduced check point fault set (see [ABRSO]) which consists of six stuck-at faults (SAF), AO,Al,Bl,CO,Cl,Dl...
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41 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Parallel-pattern simulation [ 19 ] is used to speed up the process in which 32 candidate sequences from the population are simulated simultaneously, with values bit-packed into 32-bit words....
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41 citations
Cites background from "Digital Systems Testing and Testabl..."
...1 Self-Test in MuxTree Any literature search, however superficial, on the subject of testing will reveal the existence of a considerable variety of approaches to implementing self-test in digital circuits [1], including some that can be applied to FPGAs [2, 13, 30]....
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41 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Digital test methodology has been resting on a relatively solid ground in both theory and practice [ 1 ], [2]....
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...This is a well-known phenomenon in the digital test domain [ 1 ], [2]....
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