Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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01 Dec 1995
TL;DR: This work presents a simulation-based method for combinational design verification that aims at complete coverage of specified design errors using conventional ATPG tools, and shows how to map all the foregoing error types into SSL faults.
Abstract: We present a simulation-based method for combinational design verification that aims at complete coverage of specified design errors using conventional ATPG tools. The error models used in prior research are examined and reduced to four types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), and wrong input errors (WIEs). Conditions are derived for a gate to be completely testable for GSEs. These conditions lend to small rest sets for GSEs. Near-minimal test sets are also derived for GCEs. We analyze redundancy in design errors and relate this to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. Our experiments demonstrate that high coverage of the modeled design errors can be achieved with small test sets.
41 citations
Cites methods from "Digital Systems Testing and Testabl..."
...The simulator uses parallel-pattern evaluation and critical path tracing techniques [ 2 ]; It simulates the circuit with multiple v ectors concurrently and determines the detected errors/f aults without explicit simulation of each error/f ault....
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...Errors that make a combinational circuit sequential can be detected by a le velization procedure [ 2 ]....
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...In practice, such circuits are v erified by simulation using representative input patterns (tests) [ 2 ]....
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26 Apr 1998
TL;DR: Experimental results show the proposed efficient path selection method for path delay testing can select about one percent of the paths selected by a conventional method without decreasing fault coverage.
Abstract: In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage.
41 citations
Cites methods from "Digital Systems Testing and Testabl..."
...In order to take the variation into account, we adopt the ambiguous model [1] as a basis....
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...In this paper, we propose a path selection method, called the clustering method, which is based on the ambiguous delay model [1]....
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01 Mar 1993
TL;DR: A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described, which consists of a parametric test and a behavioral test to distinguish between faulty and useful chips.
Abstract: A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 mu m double-polysilicon CMOS technologies are presented to demonstrate the testing procedure. >
40 citations
TL;DR: In this article, the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized, is addressed.
Abstract: This article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of "don't care" conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.
40 citations
TL;DR: A fault simulation-based technique to approximate each internal signal's correcting power is used, based on a more stringent condition for identifying potential error sources, to address the problem of locating error sources in an erroneous combinational or sequential circuit.
Abstract: This paper addresses the problem of locating error sources in an erroneous combinational or sequential circuit. We use a fault simulation-based technique to approximate each internal signal's correcting power. The correcting power of a particular signal is measured in terms of the signal's correctable set, namely, the maximum set of erroneous input vectors or sequences that can be corrected by resynthesizing the signal. Only the signals that can correct every given erroneous input vector or sequence are considered as a potential error source. Our algorithm offers three major advantages over existing methods. First, unlike symbolic approaches, it is applicable for large circuits. Second, it delivers more accurate results than other simulation-based approaches because it is based on a more stringent condition for identifying potential error sources. Third, it can be generalized to identify multiple errors theoretically. Experimental results on diagnosing combinational and sequential circuits with one and two random errors are presented to show the effectiveness and efficiency of this new approach.
40 citations