Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Patent•
19 Aug 1996TL;DR: In this article, a method and apparatus for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration is presented, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins.
Abstract: A method and apparatus is presented for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration. The user enters basic pin information for the integrated circuit under consideration, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins. The user connects the pins of a sample integrated circuit to the test channels of the apparatus of the invention. The apparatus of the present invention operates in accordance with the method of the present invention automatically to determine: (1) the length of the instruction register; (2) the length of the boundary scan data register; (3) which pins of the integrated circuit are outputs and which pins are inputs, and which are I/O or tri-state outputs; (4) the order that the pins are represented in the boundary scan data register; (5) the identity of the control cells in the boundary scan data register that control I/O and tri-state pins, along with which pins each controls and the sign of the control; (6) the identity of the SAMPLE/PRELOAD instruction; and (7) the identity of the IDCODE instruction and ID code, if present. These parameters are expressed in standard language in a boundary-scan description language file for the integrated circuit under investigation, thus facilitating the use of known automatic program generation software to create test programs.
40 citations
TL;DR: It is demonstrated how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches to efficient utilization of the inherent parallelism of multi-core architectures.
Abstract: Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.
40 citations
Cites background from "Digital Systems Testing and Testabl..."
...Semiconductor manufacturing processes are yield processes: a significant fraction of manufactured microchips are defective [ 1 ]....
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TL;DR: This work proposes a succinct QBF encoding for modeling sequential circuit behavior, which shows memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques.
Abstract: Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance. Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are used to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach. Extensive experiments on OpenCore circuits show memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16 percent. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.
40 citations
Cites background from "Digital Systems Testing and Testabl..."
...Today, major phases of the Very Large Scale Integration (VLSI) design flow, such as synthesis [1], placement/routing [2], verification [3] and test [4], have been fully or partially automated....
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05 May 1996
TL;DR: An Automatic Test Generation (ATG) based technique to efficiently estimate maximum power dissipation in sequential circuits is presented and shows that the ATG-based estimation is superior to traditional simulation-based technique in both speed and performance.
Abstract: With the high demand for reliability and performance, accurate estimation of maximum instantaneous power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and optimizing the power and ground routing. However, the problem of determining the input patterns to induce maximum current, and hence, the maximum power, is NP-complete. In this paper, we present an Automatic Test Generation (ATG) based technique to efficiently estimate maximum power dissipation in sequential circuits. The technique can generate tight lower bounds of maximum instantaneous power within very short CPU time compared to random simulation based techniques. In addition, we also generate the measure of the quality or effectiveness of our approach from, a statistical point of view. Experiments were performed on ISCAS-89 sequential circuit benchmarks. Results show that the ATG-based estimation is superior to traditional simulation-based technique in both speed and performance. For large circuits, the ATG approach is on an average 29% better and 37099% faster than simulation based technique.
39 citations
18 Jul 2003
TL;DR: In this article, a new mixed-mode test pattern generator is proposed with reduced power dissipation during test when compared with existing test pattern generators, which is achieved by combining the masking properties of AND/OR composition with LFSR reseeding.
Abstract: Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducing power dissipation in mixed-mode BIST. A new mixed-mode test pattern generator is proposed with reduced power dissipation during test when compared with existing test pattern generators. This is achieved by combining the masking properties of AND/OR composition with LFSR reseeding. Extensive experiments were performed on several benchmark circuits using commercial synthesis and simulation tools to validate the efficiency and assess the overhead of the proposed solution. Experimental results show that reductions up to 20% in average power dissipation during test can be achieved when compared with traditional test pattern generators.
39 citations