Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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01 May 2005
TL;DR: Experimental results show the effectiveness of the novel low-capture-power X-filling method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
Abstract: Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
183 citations
17 Mar 1997
TL;DR: A new method for state justification is proposed for sequential circuit test generation, using the linear list of states dynamically obtained during the derivation of test vectors to guide the search during state justification.
Abstract: This research was supported in part by the Semiconductor Research Corporation under contract SRC 96-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.
182 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Therefore, parallelpattern simulation [20] is used to speed up the process....
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19 Aug 2010
TL;DR: In this article, the authors discuss the emerging paradigm of variation-tolerant adaptive design for both logic and memories, and present circuit and microarchitectural techniques to perform reliable computations in an unreliable environment.
Abstract: Variations in process parameters affect the operation of integrated circuits (ICs) and pose a significant threat to the continued scaling of transistor dimensions. Such parameter variations, however, tend to affect logic and memory circuits in different ways. In logic, this fluctuation in device geometries might prevent them from meeting timing and power constraints and degrade the parametric yield. Memories, on the other hand, experience stability failures on account of such variations. Process limitations are not exhibited as physical disparities only; transistors experience temporal device degradation as well. Such issues are expected to further worsen with technology scaling. Resolving the problems of traditional Si-based technologies by employing non-Si alternatives may not present a viable solution; the non-Si miniature devices are expected to suffer the ill-effects of process/temporal variations as well. To circumvent these nonidealities, there is a need to design ICs that can adapt themselves to operate correctly under the presence of such inconsistencies. In this paper, we first provide an overview of the process variations and time-dependent degradation mechanisms. Next, we discuss the emerging paradigm of variation-tolerant adaptive design for both logic and memories. Interestingly, these resiliency techniques transcend several design abstraction levels-we present circuit and microarchitectural techniques to perform reliable computations in an unreliable environment.
182 citations
TL;DR: A new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) to provide redundant backup for several types of components.
Abstract: Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) The physical design is partitioned into a set of tiles In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead
171 citations
Cites methods from "Digital Systems Testing and Testabl..."
...We assume a widely used single stuck at, open, or short fault model [3]....
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TL;DR: It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault.
Abstract: A automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds, Three new cost functions, namely transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23.
166 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...In order to achieve this, two procedures in the original PODEM, Backtrace() and Objective() [ 1 ], are modified....
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...3.2 Transition Observability Cost In the PODEM ATPG [5], [ 1 ], at the beginning of each test generation step, a vector Tt is initialized to x, x, …, x, where x represents either an unknown or a don’t care value....
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...The proposed PODEM initializes the fault list to contain all checkpoint faults [ 1 ]....
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...A detailed description of this algorithm can also be found in [ 1 ]....
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...At any intermediate step, all gates whose output values are currently x but that have error value(s) at one or more of their inputs are said to belong to the D-frontier [5], [ 1 ]....
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