Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: The purpose of this paper is to present a comprehensive overview of the most prominent DFX techniques with respect to sustainability dimension as well as the cost ownership and product differentiation strategies.
Abstract: Managing the new product development (NPD) is a challenging mission, and most researches would argue that design is fundamentally linked to intentional action and it cannot emerge out of complexity. In fact, its complexity is generated by a large number of entities and actors which cooperate simultaneously with an unpredictable way to understand what customers want and then design product with diverse objectives in mind. A slight change in one activity may cause tremors everywhere. Within a dynamic environment and in order to meet concurrently these challenges, several researchers have implemented design for X (DFX) techniques. Regarding the availability of numerous DFX, the decision as to which one to apply remains absent. Hence, the purpose of this paper is to present a comprehensive overview of the most prominent DFX techniques with respect to sustainability dimension as well as the cost ownership and product differentiation strategies. In addition to that, complex product necessitates the consideration of integrated DFX to optimize product life cycle from a more holistic perspective. In this respect, the paper addresses a systematic review from 1980 to 2018 by investigating and discussing the past and current research of each DFX techniques as well as for integrated ones. The key problems and issues that future DFX research should address have been identified and discussed in this paper.
38 citations
16 Feb 2004
TL;DR: A method for translating Boolean circuits to CNF is presented by identifying trees of ITE operators, where each ITE has fanout count of 1, and representing every such tree with a single set of equivalent CNF clauses without intermediate variables for ITE outputs, except for the tree output.
Abstract: The paper presents a method for translating Boolean circuits to CNF by identifying trees of ITE operators, where each ITE has fanout count of 1, and representing every such tree with a single set of equivalent CNF clauses without intermediate variables for ITE outputs, except for the tree output. This not only eliminates intermediate variables, but also reduces the number of clauses, compared to conventional translation to CNF, where each ITE is assigned an output variable and is represented with a separate set of clauses. Other gates with fanout count of 1 are similarly merged with their fanout gate to generate a single set of equivalent clauses. This translation to CNF was implemented in a decision procedure for the logic of equality with uninterpreted functions and memories (EUFM), and was applied to formulas from formal verification of microprocessors. To increase the number of ITE-trees in the Boolean formulas, the decision procedure was optimized to preserve the ITE-tree structure of arguments to equality comparisons. In conventional translation to CNF with the unoptimized decision procedure, the benchmark formulas require up to hundreds of thousands of CNF variables and millions of clauses. The best translation strategy reduced the CNF variables by up to 8x; the clauses by up to 17x; the SAT-solver decisions by up to 79x; the SAT-solver conflicts by up to 96x; and accelerated the SAT solving by up to 420x.
38 citations
Cites methods from "Digital Systems Testing and Testabl..."
...This translation to CNF was implemented in a decision procedure for the logic of Equality with Uninterpreted Functions and Memories (EUFM), and was applied to formulas from formal verification of microprocessors....
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TL;DR: The architecture of a new SAT solver using reconfigurable logic and a virtual logic scheme is presented, which includes new forms of massive fine-grain parallelism, structured design techniques based on iterative logic arrays, and a decomposition technique that creates independent subproblems that may be concurrently solved by unconnected FPGAs.
Abstract: In this paper, we present the architecture of a new SAT solver using reconfigurable logic and a virtual logic scheme. Our main contributions include new forms of massive fine-grain parallelism, structured design techniques based on iterative logic arrays that reduce compilation times from hours to minutes, and a decomposition technique that creates independent subproblems that may be concurrently solved by unconnected FPGAs. The decomposition technique is the basis of the virtual logic scheme, since it allows solving problems that exceed the hardware capacity. Our architecture is easily scalable. Our results show several orders of magnitude speedup compared with a state-of-the-art software implementation, and also with respect to prior SAT solvers using reconfigurable hardware.
38 citations
Cites background from "Digital Systems Testing and Testabl..."
...For example, in ATPG, full specification would preclude test set compaction [ 1 ], and may also preclude the generation of the obtained vector by a different circuit....
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TL;DR: How fault tuples can and have been used to enhance testing tasks such as fault simulation, test generation, and diagnosis, and enable new capabilities such as interfault collapsing and application-based quality metrics is described.
Abstract: Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior of arbitrary defects in digital circuits. To justify this claim, this paper describes two types of logic faults (state transition and signal line faults) and formally shows how fault tuples can be used to precisely represent any number of faults of this kind. The capability of fault tuples to capture misbehaviors beyond logic faults is then illustrated using many examples of varying degree of complexity. In particular, the ability of fault tuples to modulate fault controllability and observability is examined. Finally, it is described how fault tuples can and have been used to enhance testing tasks such as fault simulation, test generation, and diagnosis, and enable new capabilities such as interfault collapsing and application-based quality metrics
38 citations
Cites background from "Digital Systems Testing and Testabl..."
...Finally, in Section VI, we summarize our contributions....
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Patent•
03 Dec 2002TL;DR: In this article, an external tester is arranged external to a device under test (DUT), which is operable to input test data to the DUT, receive output data from the device, and generate a signature for at least a portion of such received output data.
Abstract: A system and method that enables testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. The external tester compares the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data can be written to an error map log. Preferably, further interaction with the DUT is not required after detecting that a generated signature fails to match an expected signature in order to perform such error evaluation. Thus, error evaluation can be performed concurrently with testing of the DUT. Mask data may be stored in a compressed form, and decompressed and used for masking certain non-deterministic output bits in generating the signature.
38 citations