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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
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Proceedings ArticleDOI
Gefu Xu1, A.D. Singh
21 May 2006
TL;DR: This work presents a low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge to support full LOS testing.
Abstract: Most scan based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but require a fast scan enable. We present a low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge. Our new design is much more efficient when compared to other recent proposals, and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve TDF coverage approaching 95% for the ISCAS89 benchmarks

38 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...This scheme results in large area overheads on the data paths from the TPG to the control points and from the observation points to the ORA....

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  • ...The ORA is used to analyze the output response and .ag defective circuits....

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  • ...The BILBO gives no .exibility to designers on the TPG and the ORA, but the B2IST does....

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  • ...A multiple input signature register (MISR) is the most well known ORA....

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  • ...A single data line makes it feasible to move the TPG and the ORA to other locations....

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Proceedings ArticleDOI
06 Jun 1994
TL;DR: Test-point insertion is done to reduce the number of paths, using a time-efficient procedure, and also reducesThe number of tests and renders untestable paths testable.
Abstract: We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. Experimental results are presented to demonstrate the effectiveness of the method proposed in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

38 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...Implementations of test points that support this view can be found in [26]....

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  • ...The proposed method consists of placing test points [26] in...

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  • ...A test point placed on a line is assumed to make both controllable and observable [26]....

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Proceedings ArticleDOI
05 Jan 2009
TL;DR: The automatic test pattern generator TIGUAN is presented based on a thread-parallel SAT solver which supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck- at faults which allows to generate patterns for non-standard fault models.
Abstract: We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.

38 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Semiconductor manufacturing processes are yield processes: a significant fraction of manufactured microchips are defective [1]....

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Patent
Xijiang Lin1, Kun-Han Tsai2, Mark Kassab1, Chen Wang1, Janusz Rajski1 
31 Oct 2011
TL;DR: In this paper, a timing-aware automatic test pattern generation (ATPG) is proposed to improve the quality of a test set generated for detecting delay defects or holding time defects.
Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

37 citations

Journal ArticleDOI
TL;DR: Current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification are described.
Abstract: Test development automation tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in the article is on automatic test-pattern-generation tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boolean domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consumption. As design trends move toward nanometer technology however, new ATPG problems are emerging. Current modeling and vector generation techniques must give way to new techniques that consider timing information during test generation, scale to larger designs, and can capture extreme design conditions. The authors describe current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification.

37 citations