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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
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Proceedings Article•DOI•
21 Oct 1995
TL;DR: A new simulation-based fault modeling methodology is proposed that uses the contamination-defect-fault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions.
Abstract: This paper proposes a new simulation-based fault modeling methodology. The methodology-an extension of Inductive Fault Analysis-uses the contamination-defect-fault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions. The application of this methodology (called Inductive Contamination Analysis) is demonstrated by development of SRAM fault models.

36 citations

Book Chapter•DOI•
01 Jan 2004
TL;DR: A method for improving the fault-tolerance of cache coherent multiprocessors by dynamically verifying coherence operations in hardware, errors caused by manufacturing faults, soft errors, and design mistakes can be detected.
Abstract: A method for improving the fault-tolerance of cache coherent multiprocessors is proposed. By dynamically verifying coherence operations in hardware, errors caused by manufacturing faults, soft errors, and design mistakes can be detected. Analogous to the DIVA concept for single-processor systems, a simple version of the protocol functions as a checker for the aggressive implementation. An example implementation is shown, and the overhead is estimated for a small SMP system.

36 citations

Proceedings Article•DOI•
29 Mar 2001
TL;DR: A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described, based on evaluation of faulty functions in cones of dominator gates of fault pairs, and stem-branch equivalences for reconvergent stems and their branches are identified efficiently.
Abstract: A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Equivalence is proved without the previously required circuit transformations. Stem-branch equivalences for reconvergent stems and their branches are identified efficiently obviating the need to check for non-masking and multiple-path sensitization. Both static and dynamic techniques are developed to exploit relations among inputs of dominator cones. This reduces the simulation time required by the procedure and enables evaluation of larger cones than could be evaluated earlier. As a result, more equivalent fault pairs are identified. Experiments performed on ISCAS85 circuits and full scan ISCAS89 circuits are used to demonstrate the effectiveness of the proposed techniques.

36 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Structural analysis [6] requires circuit graph manipulation, and is useful for fanout free regions of the circuit [7]....

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  • ...Similarly, combinations (0, 1) and(1, 0) at identical inputs (IN[7],IN[9]) are not justifiable....

    [...]

Proceedings Article•DOI•
A. Attarha1, Mehrdad Nourani•
28 Apr 2002
TL;DR: A test pattern generation algorithm aiming at signal integrity faults on long interconnects is presented by considering the effect of inputs and parasitic RLC elements of the interconnect by model order reduction methodology.
Abstract: In this paper we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.

36 citations

Proceedings Article•DOI•
27 Apr 1997
TL;DR: A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator by utilizing circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort.
Abstract: A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.

36 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...First, a technique to rapidly identify states that are impossible to justify with three-valued logic [1] is presented....

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  • ...Next, a technique to rapidly identify states that are impossible to justify with three-valued logic [1] is presented....

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  • ...Sometimes it is not necessary to find illegal states; finding states that are impossible to traverse with three-valued logic simulation [1] can be sufficient to speed-up diagnostic ATPG or conventional ATPG, and can even be used for selecting partial-scan elements [12, 14]....

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