Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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19 Nov 2001
TL;DR: Several methods to reduce the run time and memory requirements of a procedure used to efficiently identify untestable path delay faults are proposed in this work.
Abstract: Several methods to reduce the run time and memory requirements of a procedure used to efficiently identify untestable path delay faults are proposed in this work. Based on the correlation between the conditions required for sensitizing subpaths in the fan-out-free regions of a circuit, equivalence relations between the subpaths are defined. Equivalence relations are used to reduce the number of subpaths considered in the identification of untestable paths. Dynamic pruning of the potential search space for identifying pairs of subpaths that cannot be sensitized together is used to achieve additional speedup. Results on benchmark circuits show the effectiveness of the proposed methods.
36 citations
02 Dec 1998
TL;DR: An approach to test generation using time expansion models that can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency is presented.
Abstract: We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We performed experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency.
36 citations
01 Nov 1997
TL;DR: Three new designs of a shift register latch that lend themselves to distributed self-test and delay test are described, with advantages of faster application of test vectors, higher DC and AC fault coverages, with low performance impact.
Abstract: This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.
36 citations
TL;DR: Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques.
Abstract: Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. Three simulation-based techniques for dynamic compaction of test sequences are described. The first technique uses a fault simulator to remove test vectors from the test sequence generated by a test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in a partially-specified test sequence in order to increase the number of faults detected by the sequence. The third technique uses test sequences provided by the test generator as seeds in a genetic algorithm, and better sequences are evolved that detect more faults. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques.
36 citations
Cites background from "Digital Systems Testing and Testabl..."
...Another approach is to generate a set of partially-specified test vectors and, then, merge compatible test vectors [ 9 ]....
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TL;DR: Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models.
Abstract: New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good lower bounds on these measures, as well as providing the actual input vectors that attain such bounds. Automatic generation of a functional vector loop for near-worst case power consumption is also attained. Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models.
36 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Parallel-pattern simulation [10] is used to speed up the process; thus, 32 individuals from the population are simulated simultaneously, with values bit-packed into 32-bit words....
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