Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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10 Jun 2010
TL;DR: This paper develops a comprehensive set of mutation operators for concurrency constructs in SystemC and defines a novel concurrent coverage metric considering multiple execution schedules that a concurrent program can generate.
Abstract: Design verification has grown to dominate the cost of electronic system design; however, designs continue to be released with latent bugs. A verification test suite developed for a sequential program is not adequate for a concurrent program. A major problem with design verification of concurrent systems is the lack of good coverage metrics. Coverage metrics are heuristic measures of the exhaustiveness of a test suite. High coverage, in general, implies fewer bugs. SystemC is the most popular concurrent system level modeling language used for designing SoCs in the industry. We propose to attack the verification quality problem for concurrent SystemC programs by developing novel mutation testing based coverage metrics. Mutation testing has successfully been applied in software testing and RTL designs. In this paper, we develop a comprehensive set of mutation operators for concurrency constructs in SystemC. Our approach is also unique in that we define a novel concurrent coverage metric considering multiple execution schedules that a concurrent program can generate. This metric allows us to adequately measure the coverage for concurrent programs. We performed experiments with various designs including a large industrial design and obtained favorable results on multiple applications.
35 citations
Cites background from "Digital Systems Testing and Testabl..."
...In this example, thread T2 is waiting for an event from thread T1 to move forward. cs1 and cs2 are outputs of the design and are initially true(t), false(f), respectively....
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03 Oct 2000
TL;DR: Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup and test set compaction of 60% when faults of all types are analyzed simultaneously.
Abstract: A test generation tool for combinational circuits called FATGEN has been developed based on the notion of fault tuples. FATGEN can be used to simultaneously generate tests for many types of misbehavior that occur in digital systems. Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup of nearly 32% and test set compaction of 60% when faults of all types are analyzed simultaneously. In addition, there is an average reduction of approximately 34% in the number of aborted faults.
35 citations
03 Oct 2000
TL;DR: A BIST-based approach able to detect and accurately diagnose any single and most multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) and identify its internal faulty modules or modes of operation provides the basis for both failure analysis and repair strategy for fault-tolerance.
Abstract: We present a BIST-based approach able to detect and accurately diagnose any single and most multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs). For any faulty PLB, we also identify its internal faulty modules or modes of operation. This accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs.
35 citations
TL;DR: This paper proposes a publicly detectable watermarking scheme to bridge the gap between IP protection and IP management, and shows that the proposed watermarked designs have low design overheads, and the probabilities of coincidence and removal reduce rapidly with increased watermark and scan chain length.
Abstract: Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing design, and is vulnerable to removal attack as the test logic is independent of the functional logic. In this paper, we propose a publicly detectable watermarking scheme to bridge the gap between IP protection and IP management. The design is watermarked by means of synthesis-for-testability (SfT), where the test and functional logics of the IP are merged and synthesized together without using scannable flip-flops. Watermarked constraints are imposed on the scan chain ordering problem in the SfT process so that ownership of the embedded IP can be publicly identified by lawful IP providers, buyers and consumers by injecting a specific test vector in the field. The overhead due to the watermark insertion is minimized by a nearest neighbor search algorithm for flip-flop reordering. As the scan function is an integral part of the design in the synthesis process of the IP creation, the watermark is harder to be removed relative to other scan chain watermarking schemes whose test circuits are logically independent of the IP functionality. To deter and track IP fraudulence by the licensees, a provable mechanism is proposed to enable multiple authorships of different IP cores in a single chip to be publicly authenticated in the field. Experiments performed with ISCAS89 and LGSyn93 benchmark circuits show that the proposed watermarked designs have low design overheads, and the probabilities of coincidence and removal reduce rapidly with increased watermark and scan chain length.
35 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Normally, the test structure is added after the circuit under test (CUT) has been synthesized [29]....
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...Scan design [29]–[33] is typically used to make direct access to internal circuit nodes to overcome the difficulty of automatic test pattern generation for sequential circuits....
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IBM1
TL;DR: The sheer number of design rules has been growing at a rapid pace with every technology generation, and more process constraints have required automatic migration of layouts from one technology generation to next, especially for custom layouts.
Abstract: This chapter discusses yield loss mechanisms, yield analysis and common physical design methods to improve yield. Yield optimization methods work with the measure, model, and mitigate flow. Root cause analysis of failures is a necessary component of the yield improvement and process ramp-up process. Yield prediction requires modeling of various complicated physical and statistical phenomena. The yield analysis problem can be decomposed into the analysis of parametric and catastrophic failures. The analysis of chip failures and consequent yield loss is an active area of research, and there is little consensus on yield metrics and calculation methods in process-variability regime. The extraction of critical area for various types of faults poses the major computational bottleneck in very large scale integration random yield prediction. Back-end-of-the-line yield and manufacturability optimization is a complicated task. Redundant via insertion provides another effective way of increasing design reliability and yield.
35 citations
Additional excerpts
...For a more detailed discussion, see [4]....
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