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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Proceedings ArticleDOI
28 Feb 1994
TL;DR: The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints and it is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing.
Abstract: Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large Built-in self-test (BIST) schemes are attractive for such comprehensive testing The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing Also, CA are shown to be better TPGs than LFSRs for two-pattern testing Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs >

34 citations

Journal ArticleDOI
TL;DR: An extensible fault model for the implementation of transformations based on common programmer faults and the technicalities of graph transformations is proposed and integrated into traditional hardware testing and software testing techniques for generating test cases.

34 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...For its simplicity, the method of Boolean differences [16,21] is applied here which generates binary test vectors for stuck-at-faults in the combinational circuit representing the pattern matching....

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Patent
29 Mar 1993
TL;DR: In this article, the authors propose a method to automatically generate test vector sequences for proper assembly of complex custom IC's onto printed circuit boards using goal-seeking and minimization procedures.
Abstract: Method and apparatus for preparing sequences of test vectors to test for proper assembly of complex custom IC's onto printed circuit boards. The method, operating with appropriate apparatus for driving and sensing pins of a sample IC, automatically prepares an in-circuit test vector sequence, starting with only rudimentary information about the pins of the IC and no information at all about the functions or internal structure of the IC. The method makes use of goal-seeking and minimization procedures. The goal-seeking procedure constructs vector sequences from pseudorandom numbers until it finds a sequence which effectively and stably attains a set of pin fault coverage goals stated by the human operator. The minimization procedure then shortens the sequence, discarding excess vectors and keeping only those which efficiently contribute to the attainment of the pin fault coverage goal. The human operator may suggest sets of goals and starting sets of vectors, and may define clock events and data exchange cycles of multiple vectors in order to give the process a head start. The vectors are translated into a form suitable for incorporation into the programs of popular in-circuit ATE.

34 citations

Proceedings ArticleDOI
12 Mar 2015
TL;DR: A novel protection scheme, called Entanglement, which can substantially strengthen the Design Withholding framework, and is distinguished from the previous works by not relying on the difficulty of finding the solution for some NP-Complete/NP-Hard problems, but rather, on the exponentially boosted number of problems that an attacker has to solve.
Abstract: Globalization of the semiconductor industry has raised serious concerns about trustworthy hardware. Particularly, an untrusted manufacturer can steal the information of a design (Reverse Engineering), and/or produce extra chips illegally (IC Piracy). Among many candidates that address these attacks, Design Withholding techniques work by replacing a part of the design with a reconfigurable block on chip, so that none of the manufactured chips will function properly until they are activated in a trusted facility, where the withheld function is restored back into the reconfigurable block on chip. However, most existing approaches are ad-hoc based, and are facing two major challenges: 1) susceptibility to a category of algorithmic attacks, from attackers in a strong position, such as a manufacturer; and 2) scaling up the defense level is checkmated by the explosion of hardware cost that has to be paid at the designer's side. In this paper, we propose a novel protection scheme, called Entanglement, which can substantially strengthen the Design Withholding framework: 1) the algorithmic attacks are prevented by forcing the attacker to solve a huge number of problems of high computational complexity; 2) the attack cost (in terms of computational complexity) is quantitatively controllable at the designer's end, with low hardware overhead: while the cost of attack can be increased exponentially, the hardware overhead imposed on the designer's side grows only linearly. The proposed work distinguishes itself from the previous works by not relying on the difficulty of finding the solution for some NP-Complete/NP-Hard problems, but rather, on the exponentially boosted number of such problems that an attacker has to solve, while carefully maintaining the growth of the hardware overhead to be scalable via Entanglement.

34 citations


Additional excerpts

  • ...This problem is equivalent to the classical problem of Automatic Test Pattern Generation (ATPG) in IC testing, which is of NP-Complete complexity [11]....

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Journal ArticleDOI
TL;DR: The proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing and can be equally well utilized for manufacturing and concurrent on-lineTesting in the field.
Abstract: Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

34 citations