Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: A heuristic method to generate test sequences which create worst-case power drop by accumulating the high-frequency and low-frequency effects by employing a dynamically constrained version of the classical D-algorithm for test generation.
Abstract: High-performance digital ICs manufactured in deep-submicron technologies tend to draw considerable amounts of power during operation. Power droop describes the impact of power consumption transients on the logic values of a circuit's signal lines and, ultimately, on the correctness of the circuit's operation. Although power droop could cause an IC to fail, such failures cannot be screened during testing, because conventional fault models do not cover them. In this article, we present a technique for screening such failures. We propose a heuristic method to generate test sequences that create worst-case power drop by accumulating high- and low-frequency effects. We employ a dynamically constrained version of the classical D-algorithm, which generates new constraints on the fly, for test generation. The obtained patterns can be used for manufacturing test and early silicon validation. We have implemented a prototype ATPG to demonstrate the feasibility of this approach.
33 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Unfolding is the standard approach for sequential test generation [37]....
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...The proposed method to generate a test sequence for power droop is based on the D-algorithm, which is a fundamental ATPG method [36, 37]....
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TL;DR: A voltage scaling technique to minimize the power consumption of a combinational circuit using the converter-free multiple-voltage structures and an efficient heuristic algorithm to solve it is described.
Abstract: Recent research has shown that voltage scaling is a very effective technique for low-power design. This paper describes a voltage scaling technique to minimize the power consumption of a combinational circuit. First, the converter-free multiple-voltage (CFMV) structures are proposed, including the p-type, the n-type, and the two-way CFMV structures. The CFMV structures make use of multiple supply voltages and do not require level converters. In contrast, previous works employing multiple supply voltages need level converters to prevent static currents, which may result in large power consumption. In addition, the CFMV structures group the gates with the same supply voltage in a cluster to reduce the complexity of placement and routing for the subsequent physical layout stage. Next, we formulated the problem and proposed an efficient heuristic algorithm to solve it. The heuristic algorithm has been implemented in C and experiments were performed on the ISCAS85 circuits to demonstrate the effectiveness of our approach.
33 citations
Cites background from "Digital Systems Testing and Testabl..."
...Definition 5 (Depth): Similar to the definition of level in [14], we can define the depth of a vertex u in a graph G to be the number of edges in the longest path from u to a sink of G....
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07 Nov 1993
TL;DR: A novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device and demonstrate test time reductions as large as 75% over traditional test schemes at the expense of 1-3 multipliers.
Abstract: A major drawback in using scan techniques is the long test application times needed to shift test data in and out of a device. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device. The main idea is to employ multiplexers to bypass registers that are not frequently accessed in the test process and hence reduce the overall test time. For partitioned scan designs, we describe two different modes of test application which can be used to efficiently tradeoff the logic and routing overheads of the reconfiguration strategy with the test application time. In each case, we provide optimization techniques to minimize the number of added multiplexers and the corresponding test time. Implementation results demonstrate test time reductions as large as 75% over traditional test schemes at the expense of 1-3 multipliers.
33 citations
01 Jan 1994
TL;DR: This work presents a technique for testing self-timed micropipelines for stuck-at faults and for delay faults in the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing.
Abstract: Micropipelines, self-timed event-driven pipelines, are an attractive way of structuring asynchronous systems that exhibit many of the advantages of general asynchronous systems, but enough structure to make the design of significant systems practical. As with any design method, testing is critical. We present a technique for testing self-timed micropipelines for stuck-at faults and for delay faults in the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing. This scan path allows the processing logic in the micropipeline, as well as the control of the micropipeline, to be fully tested with only a small overhead an the latch and control circuits. The test method is very similar to scan testing in synchronous systems, but the micropipeline retains its self-timed behavior during normal operation.
33 citations
15 Dec 1994
TL;DR: A fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational and sequential circuits and the incremental concept is extended to sequential test generation, and ISAT (Incremental Sequential ATPG) is developed.
Abstract: Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage This thesis presents time efficient ATPG systems for combinational and sequential circuits
First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT) At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses
Further, for concurrent engineering design environments, an incremental ATPG concept is introduced When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to speed up test generation for the new circuit Four incremental techniques are developed to utilize information from the original tests These four techniques and a fast deterministic test generation algorithm are combined to give ICAT (Incremental Combinational ATPG) ICAT speeds up ATPG by up to a factor of fifteen
In sequential test generation, a fast, efficient deterministic test generation algorithm, called Sequential ATPG (SAT), is developed SAT employs two complementary procedures: a new improved forward procedure and a simplified backward procedure Each procedure compensates for the disadvantages of the other Benchmark results show SAT is a fast algorithm and produces high fault coverage with a reasonable number of test vectors More important, SAT is a consistent algorithm that can handle difficult circuits not handled well by other algorithms as well as easy circuits
Finally, the incremental concept is extended to sequential test generation, and ISAT (Incremental Sequential ATPG) is developed In ISAT, to take advantage of information from the original tests by the backward method, the order of application of the forward and backward procedures is reversed Benchmark results indicate that ISAT improves test generation time for many cases
33 citations