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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Proceedings Article•DOI•
26 Apr 1998
TL;DR: An extension of the n-detection model is proposed that alleviates the problem of the same set of faults to be detected by several different tests, by considering m-tuples of faults and requiring that different tests would detect different m- tuples.
Abstract: N-detection stuck-at test sets were shown to be effective in achieving high defect coverages for benchmark circuits. However, the definition of n-detection rest sets allows the same set of faults to be detected by several different tests, thus potentially detecting the same defects. We propose an extension of the n-detection model that alleviates this problem by considering m-tuples of faults and requiring that different tests would detect different m-tuples. We present experimental results to support this model.

31 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Note that an m-tuple fault is different from a multiple stuck-at fault where several stuck-at faults are assumed to be simultaneously present [5]....

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Journal Article•DOI•
TL;DR: A mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay is developed.
Abstract: Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.

31 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...The digital part deals with controllability and observability measures [21], and is used to break ties....

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Proceedings Article•DOI•
21 Jan 2003
TL;DR: The area overhead resulting from addition of a scan-chain based watch-point logic is discussed and is compared with other proposed debugging techniques.
Abstract: This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watch-point conditions and thus is very fast. In this paper, the area overhead resulting from addition of a scan-chain based watch-point logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.

31 citations

Journal Article•DOI•
TL;DR: New methods for fault-effect propagation and state justification that use finite-state-machine sequences that use genetic-algorithm-based techniques are proposed for sequential circuit test generation.
Abstract: New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing sequences are used to propagate the fault effects from the flip-flops to the primary outputs by distinguishing the faulty machine state from the fault-free machine state. Set, clear, and pseudoregister justification sequences are used for state justification via a combination of partial state justification solutions. Reengineering of existing finite-state machine sequences may be needed for specific target faults. Moreover, conflicts imposed by the use of multiple sequences may need to be resolved. Genetic-algorithm-based techniques are used to perform these tasks. Very high fault coverages have been obtained as a result of this technique.

31 citations

Journal Article•DOI•
TL;DR: This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits.
Abstract: This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

31 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...Most of these methods work at the later stages of the design process, where improving testability usually requires large area and delay overheads [ 2 ]....

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