Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
More filters
05 Nov 2012
TL;DR: A new failure dependent design partitioning method is proposed to improve volume diagnosis throughput with a minimal impact on diagnosis quality to increase the throughput of volume diagnosis by increasing the number of failing dies diagnosed within a given time.
Abstract: A method based on dynamic design partition is presented to increase the throughput of volume diagnosis by increasing the number of failing dies diagnosed within a given time T using given constrained computational resources C. Recently we proposed a static design partitioning method to reduce the diagnosis memory footprint for large designs [1] to achieve this objective. The method in [1] is applied once for each design without using the information of test patterns and failure files, and then diagnosis is performed on an appropriate block(s) of the design partition for a failure file. Even though the memory footprint of diagnosis is reduced the diagnosis quality is impacted to unacceptable levels for some types of defects such as bridges. In this paper, we propose a new failure dependent design partitioning method to improve volume diagnosis throughput with a minimal impact on diagnosis quality. For each failure file, the proposed method first determines the small partition needed to diagnose this failure, and then performs the diagnosis on this partition instead of the complete design. Since the partition is far smaller, both the run time and the memory usage of diagnosis can be significantly reduced better than when earlier proposed static partition is used. Extensive experiments were conducted on several large industrial designs to validate the proposed method. It has been observed that the typical partition size for various defects is less than 3% of the size of the original design. Also diagnosis runs much faster (>2X) on the partition. Combining these two factors, the throughput of volume diagnosis can be improved by an order of magnitude.
31Â citations
TL;DR: In this article, an OTA-C low-pass filter with a passband from 0 to 4.5 MHz was designed and a current-mode method for the error detection of this filter was proposed.
Abstract: Analog filters are important building blocks of many communication and instrumentation systems. However, similar to other analog circuits, testing an analog filter is a difficult problem. In recent years, this problem has become even more difficult because of the increase of circuit complexity. Operational transconductance amplifier-capacitor (OTA-C) filters are especially useful in video applications such as HDTV. In this paper, we first present the design of an OTA-C low-pass filter with a passband from 0 to 4.5 MHz. We then propose a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently detected. This technique has been applied to the OTA-C filter and a testable design is obtained. Experimental results show that our design has the following advantages: (1) easy to design and implement; (2) high accuracy in error detection; (3) little impact on the circuit performance of the filter; and (4) high error-detection speed. From an actual layout, we find that the area overhead is about 25% and only one extra pin is needed.
31Â citations
Cites methods from "Digital Systems Testing and Testabl..."
...N THE past two decades, many design for testability (DFT) techniques have been successfully implemented in digital circuits, and the cost of testing has been greatly reduced by introducing testability criteria early in the design stage [ 1 ]....
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01 Dec 1995
TL;DR: A functional fault model for delay faults in combinational circuits is proposed and a functional test generation procedure based on this model is described, suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected.
Abstract: We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. It can also potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of branch and bound strategies. A parameter called /spl Delta/ is used to control the number of functional faults targeted and thus the number of tests generated. If /spl Delta/ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given function. An appropriate subset of tests can be selected once the implementation is known. The test sets generated for various values of /spl Delta/ are fault simulated on gate-level realizations to demonstrate their effectiveness.
31Â citations
Cites background from "Digital Systems Testing and Testabl..."
...Previous works on functional testing of logic faults (such as stuck-at faults) can be found in [ 2 ]....
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07 Jan 2002
TL;DR: An algorithm to model any given multiple stuck-at fault as a single stuck- at fault is given, which allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits.
Abstract: We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most n+3 modeling gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridging fault modeling, diagnosis, circuit optimization, and testing of multiply-testable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partial-scan circuits in which some lines are split, leading to a transformation of single stuck-at faults into multiple faults.
31Â citations
Cites background from "Digital Systems Testing and Testabl..."
...A single fault irredundant circuit is shown in Figure 4(a) [2]....
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07 Nov 1999
TL;DR: This work presents an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation, and derived analytical expressions, as functions of rise and fall times for the magnitude of overshoots and undershoots.
Abstract: Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13 /spl mu/m technology such noise in local interconnects embedded in combinational logic can exceed the threshold voltage. We show the impact of such noise on different kinds of circuits. The magnitude of this noise can increase due to process variations. We present an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation. To facilitate the vector generation method, we have derived analytical expressions, as functions of rise and fall times for (i) the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time required for the circuit response to settle to a bound close to the final value.
31Â citations
Cites methods from "Digital Systems Testing and Testabl..."
...This mixed-signal test generator uses a PODEM-like approach [1] and extends an existing test generator for crosstalk faults [4] by (i) considering conditions for excitation of inductance induced oscillations that reduce backtracking, and (ii) relaxing propagation conditions that subsequently increase the solution space....
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