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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Patent
27 Dec 1995
TL;DR: In this article, a synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test, and the test patterns are translated into test sequences for the asynchronous circuit.
Abstract: A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit The STM offers numerous advantages over prior art methods namely, (1) synchronous, sequential test generation techniques can be used to generate tests for the model, (2) tests generated for the STM can always be translated into tests for the asynchronous circuit under test, and (3) these tests will not suffer from test invalidation due to unstable states, because the STM enforces a fundamental mode of operation during test generation Experimental results on several benchmarks show that the STM method generates high fault coverage tests with no test invalidation

30 citations

Proceedings ArticleDOI
17 Oct 1993
TL;DR: Experimental results show that the proposed method, with no a priori test strategy assumption, can achieve higher fault coverage in shorter test generation time than an algorithm which disregards testability, and can have high testability with fewer scan registers than some design-for-test methods.
Abstract: Existing conditional resource sharing methods using in behavioral synthesis focus on area and performance optimization and do not consider testability. This paper extends our previous work to handle conditional branches. A hierarchical control-data flow graph (HCDFG) is used to model the system behavior. A postorder traversal of the HCDFG is employed to reduce sequential depths and loops for testability synthesis. Experimental results for the benchmarks show that our method, with no a priori test strategy assumption, can achieve higher fault coverage in shorter test generation time than an algorithm which disregards testability, and, with partial scan test assumption, can have high testability with fewer scan registers than some design-for-test methods. >

30 citations

Journal ArticleDOI
01 Jul 2004
TL;DR: A framework to systematically design and evaluate networking protocols based on a 'building block' approach, which discusses two case studies on utilizing the building block approach for analyzing Ad-hoc routing protocols and IP mobility protocols in a systematic manner.
Abstract: With the emergence of new application-specific sensor and Ad-hoc networks, increasingly complex and custom protocols will be designed and deployed. We propose a framework to systematically design and evaluate networking protocols based on a 'building block' approach. In this approach, each protocol is broken down into a set of parameterized modules called "building blocks", each having its own specific functionality. The properties of these building blocks and their interaction define the overall behavior of the protocol. In this paper, we aim to identify the major research challenges and questions in the building block approach. By addressing some of those questions, we point out potential directions to analyze and understand the behavior of networking protocols systematically. We discuss two case studies on utilizing the building block approach for analyzing Ad-hoc routing protocols and IP mobility protocols in a systematic manner.

30 citations

Proceedings ArticleDOI
01 Oct 2006
TL;DR: This article proposes a heuristic method to generate test sequences that create worst-case power drop by accumulating high- and low-frequency effects by employing a dynamically constrained version of the classical D-algorithm for test generation.
Abstract: Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power droop and is an instance of power supply noise. Although power droop may cause an IC to fail, such failures cannot currently be screened during testing as it is not covered by conventional fault models. In this paper we present a technique for screening such failures. We propose a heuristic method to generate test sequences which create worst-case power drop by accumulating the high-frequency and low-frequency effects. The generated patterns need to be sequential even for scan designs. We employ a dynamically constrained version of the classical D-algorithm for test generation, i.e., the algorithm generates new constraints on-the-fly depending on previous assignments. The obtained patterns can be used for manufacturing testing as well as for early silicon validation. A prototype ATPG is implemented to demonstrate the feasibility of the approach and test sequences are generated for ISCAS circuits.

30 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...Unfolding is the standard approach for sequential test generation [ 37 ]....

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  • ...The proposed method to generate a test sequence for power droop is based on the D-algorithm, which is a fundamental ATPG method [36, 37 ]....

    [...]

Proceedings ArticleDOI
28 Apr 1996
TL;DR: A dynamic diagnosis scheme for synchronous sequential circuits is proposed that combines cause-effect and effect-cause strategies and eliminates from consideration faults that could not have caused the failing symptoms.
Abstract: A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes like fault dictionaries no prior computation and storage of fault symptoms is performed. The technique combines cause-effect and effect-cause strategies. Cause-effect analysis is performed by single stuck at fault simulation followed by a matching algorithm. Effect-cause analysis is performed by an error propagation back-trace starting from the falling outputs. The error propagation back-trace eliminates from consideration faults that could not have caused the failing symptoms. The procedure is exact for defects behaving as single stuck-at faults. Experimental results are provided for the ISCAS89 benchmark circuits.

30 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...Experimental results are provided for the ISCAS89 benchmark circuits....

    [...]