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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Power Droop Testing
TL;DR: This article proposes a heuristic method to generate test sequences that create worst-case power drop by accumulating high- and low-frequency effects by employing a dynamically constrained version of the classical D-algorithm for test generation.
Journal ArticleDOI
Understanding yield losses in logic circuits
TL;DR: This work introduces an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage, and shows an adequate link between the design automation tools and the testers and correlation between the AtPG patterns and the tester failure reports.
Proceedings ArticleDOI
Hardware efficient LBIST with complementary weights
TL;DR: Experiments show that two complementary weights are sufficient for weighted random pattern testing and it presents a novel direction for exploiting weighted patterns.
Journal ArticleDOI
An observability enhancement approach for improved testability and at-speed test
TL;DR: A design-for-test method that permits at-speed testing is introduced based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator.
Proceedings ArticleDOI
Discrete event system approach for delay fault analysis in digital circuits
TL;DR: This paper presents the application of discrete event system (DES) techniques to delay fault modeling and analysis, and develops models and algorithms that provide design testability evaluation and robust delay fault test generation.