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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Proceedings ArticleDOI
13 Nov 1997
TL;DR: This paper presents a method for the testing and diagnosis of faults in FPGAs that imposes no hardware overhead, and requires minimal support from external test equipments.
Abstract: Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily tolerated once fault sites are located. In this paper we present a method for the testing and diagnosis of faults in FPGAs. The proposed method imposes no hardware overhead, and requires minimal support from external test equipments. Test time depends only on the number of faults, and is independent of the chip size. With the help of this technique, chips with faults can still be used. As a result, the chip yield can be improved and chip cost is reduced. Experimental results are given to show the feasibility of this method.

30 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...In our design, the TPG is made of a type I LFSR [9] which implements the polynomial x+x+x+x+1....

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  • ...A candidate for this purpose is BIST [9]....

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  • ...This means that the TPG must have I independent output signals, which implies I flip-flops are required: BTPG ≥ I/F (2) In practice, if two input lines do not affect the same output, they may be applied with the same signal to achieve pseudoexhaustive testing [9]....

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Proceedings ArticleDOI
26 Oct 2004
TL;DR: The main industry test trends and recent innovations in testing integrated circuits as they are applied within Philips are described.
Abstract: New process technologies, increased design complexity, and more stringent customer quality requirements drive the need for better test quality, improved test program development, and faster ramp-up at overall lower product cost. In this paper we describe the main industry test trends and recent innovations in testing integrated circuits as they are applied within Philips.

30 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...Software-based fault diagnosis techniques can be classified in two main groups [33]: cause-effect and effect-cause analysis....

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Proceedings ArticleDOI
01 Jun 1991
TL;DR: A technique is described that makes use of the Crosscheck grid of sense and probe lines to also selectively inject signals into storage elements, based on a novel design of a grid-addressable latch element, called Cross-Controlled Latch.
Abstract: The Crosscheck grid of sense and probe lines provides a convenient mechanism for addressing a large number of nodes in the circuit. This testpoint grid was previously used to observe internal nodes in the circuit. In this paper we describe a technique that makes use of the same grid to also selectively inject signals into storage elements. The technique is based on a novel design of a grid-addressable latch element, called Cross-Controlled Latch (CCL), which allows all flip-flops in the circuit to be deterministically controlled. The combination of massive observability provided by the Crosscheck test matrix and controllability completely solves the static ASIC functional test problem. In addition to the basic technique, we will discuss its area and performance impact. We present results on two real designs, as well as on several pathological cases which are known to be difficult to test. I. Introduction Automatic test generation for sequential circuits is known

30 citations

Proceedings ArticleDOI
30 Sep 2003
TL;DR: HyAC, a fast yet accurate hybrid ATPG method targeting multiple-aggressor induced crosstalk errors, inherits advantages from both Boolean- satisfiabilitity based methods and structural-based methods to achieve flexibility and efficiency.
Abstract: As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk noise generated by coupling capacitances between wires. Test vectors that activate and propagate crosstalk noise effects are becoming an essential part of design verification and manufacturing test. However, deriving such vectors is a complex task. In this paper, we propose HyAC, a fast yet accurate hybrid ATPG method targeting multiple-aggressor induced crosstalk errors. Given a victim and a set of aggressors, the proposed ATPG method searches for test vectors to activate and propagate a crosstalk error for the victim. Due to logic constraints, it may not be possible to trigger all aggressors simultaneously. Therefore, firstly we use an implication graph (IG) that consists of logic variables and structural information to check for logic conflicts. If the current set of aggressors is not feasible, our algorithm automatically searches for the next-best subset of aggressors (resulting in the largest noise). After a set of feasible aggressors is identified, we use a modified PODEM [21] algorithm to search for test vectors. This hybrid structural SAT-based ATPG method inherits advantages from both Boolean- satisfiabilitity based methods and structural-based methods to achieve flexibility and efficiency. We demonstrate the accuracy, high quality, and run time efficiency of HyAC through experiments conducted on several benchmark circuits as well as a circuit from a commercial processor.

30 citations

Proceedings ArticleDOI
25 Jun 1991
TL;DR: Experimental results demonstrate that for most circuits TSUNAMI can generate test sets for all faults in fairly small amounts of time and is very efficient for hard-to-detect and redundant faults.
Abstract: An algorithm is presented for generating tests for single stuck line faults using a combination of algebraic processing and conventional path oriented search. Unlike conventional test generation algorithms, this algorithm uses algebraic methods to determine the complete set of input assignments that will propagate an error signal through a gate in a path to a primary output. The algorithm uses ordered binary decision diagrams (BDDs) for algebraic processing. For a large number of circuits that are amenable to analysis using BDDs, the algorithm is faster than previous algebraic methods. The algorithm has been implemented as the program TSUNAMI. Experimental results demonstrate that for most circuits TSUNAMI can generate test sets for all faults in fairly small amounts of time and is very efficient for hard-to-detect and redundant faults. Moreover, since a large set of tests is generated for each fault, these sets can be compacted to a very high degree. Using benchmark circuits as a reference, TSUNAMI obtains test sets up to 70% smaller than test sets generated by conventional algorithms. >

30 citations