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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Z-sets and z-detections: circuit characteristics that simplify fault diagnosis
TL;DR: It is demonstrated that benchmark circuits as well as industrial circuits have structural characteristics and characteristics based on fault simulation that determine the numbers of fault pairs that are guaranteed to be distinguished by a given fault detection test set.
Book ChapterDOI
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination
TL;DR: This paper presents a new algorithm that completely removes the problem of false negatives by introducing normalized functions instead of free variables at cut points, which is significantly more accurate in finding cut-points, and leads to more efficient counter-example generation for incorrect circuits.
Proceedings ArticleDOI
Conflict driven techniques for improving deterministic test pattern generation
TL;DR: This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits called dynamic decision ordering, conflict driven recursive learning and conflict learning, which are incorporated into a commercial D-algorithm based ATPG tool.
Proceedings ArticleDOI
On testing delay faults in macro-based combinational circuits
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: This work considers the problem of testing for delay faults in macro-based circuits, and proposes two delay fault models that are analogous to the gate-level gross delay fault model and the Gate-level pathdelay fault model.